#!/apps/bin/perl -w
eval 'exec perl -S $0 "$@"'
    if 0;

=head1 NAME

AFETC - builds a bottom-up compile structure for DC-t using the Design Budgeter,
             PrimeTime and Floorplan Manager.  This tool is targeted to use the Avant!
             Tool flow on the back end including Planet Floorplanner and Apollo router.

=head1 SYNOPSIS

B<afetc>
B<-d> I<designlist> 
or
B<-r> I<designlist> 
[B<-m> I<Makefile> [B<-mi> I<Makefile.inc>] ] 
[B<-c> I<initcons.scr> ] 
[B<-l> I<depth> ]

=head1 DESCRIPTION

AFETC reads a design dependancy list created in DC Shell and
generates a Makefile and sundry files required to perform an automated, 
bottom-up parallel build of a given design.

=head1 OPTIONS

=over 4

=item -d designlist file

Specify the designlist file generated in Design Compiler using the DC Shell
I<write_designlist> command.

=item -r designlist file

Specify the designlist file generated rvpn for the RTL Level of the design
I<write_designlist> command.

=item -m Makefile

Specify the name of the Makefile to generate.  By default, the file "Makefile" 
is created. A Makefile include file will also be generated with the same name 
as the Makefile and a .inc extension appended. The Makefile include file will 
not be created if one with the same name is pre-existant.

=item -c initial_constraints_script

This is the name of the initial constraints file that will be generated, unless 
one with the same name is existant. This script is included by dc_shell when 
performing the pass-zero compile of the design.

This file MUST be edited by the designer before invoking Make.

This file should be replaced by the designer, if they have a better clue of
the design style and naming conventions of clocks etc., to improve speed and
quality of the pass-zero compile.

=item -l levels_to_budget_to

This specifies how far down the design hierarchy to perform seperate 
compilations.  By default the Makefile will be build to compile from 
all leaf-level modules. Setting this value to an integer less than the 
maximum levels of hierarchy in the design will cause the modules at the 
specified level to be compiled with its children in one compile.
This will also cause the Design Budgeter to only generate constraint scripts
to the specified level. 

=back

=head1 OUTPUTS

=item dc_ordered_design_list

Specifies the name of a file to create containing a DC Shell script that 
creates the DC Shell variable "TDT_ordered" containing an ordered list
of designs for compilation. This variable may be used inside a DC Shell 
foreach loop to compile designs in a correct bottom-up order.

=item dc_shell_compile_script

This is the name of a "generic" compile script that will be generated, 
unless one with the specified name is pre-existant. This script is called 
by DC Shell when performing the design compilation.

=item db_shell_budget_script

This is the name of a "generic" budgeting script that will be generated, 
unless one with the same names is existant. This script is called by 
budget_shell when performing the design budget.


=head1 DESCRIPTION

I think I already pretty-much explained what this script spits out.

The idea is to take a GTECH design (one .gdb for each design module) and
create a parallel Make to enable fast, small-memory compiles to geneate
the complete design.

=head1 EXAMPLES

afetc C<-d> TOP.designlist C<-m> Makefile ;

This will generate Makefile, and Makefile.inc files and a generic compile
script for a complete bottom-up compile of the design whose data was in
the TOP.designlist file.

To setup your directory to mimic the variables that you set in the 
I<Makefile.inc> file, you would run make as shown below.

make C<-f> Makefile setup;

To build an initial design using initial constraints, you would run make, 
something like this.

make C<-f> Makefile all PASS=0;

To budget the newly built design, you would run make like this.

make C<-f> Makefile budgets;

To re-build your design using budgeted block constraints, you would run make
something like this.

make C<-f> Makefile all_hier PASS=1;

=head1 ENVIRONMENT

All variables associated with the Makefile are defined in the Makefile.inc file.

These may all be overridden by Environment variables, IFF you specify the 
B<-e> option when invoking Make.

=head1 SEE ALSO

make(1S), dc_shell-t(1), design_analyzer(1), budget_shell(1), rvp(1), pt_shell(1)

=head1 RESTRICTIONS

This is intended only as an example of how you might use Design Budgeter
to enable a parallel make for your design environment.

=head1 AUTHOR

Thomas D. Tessier, t2design Incorporated
Special thanks to:
           Jon Baldry <baldrik@synopsys.com> Synopsys RTL Synthesis CAE
Who provided the idea and the baseline scripts.

=cut

## 
## $Id: ipx:syn:bin:build_make.pl,v 1.69 2000-07-17 11:05:47-06 tessitd Exp $
##
## This script builds the baseline compile and constraint scripts and 
##  a makefile suitable to use for Synthesis using the Synopsys Design 
##  Budgeting approach.
##
##

### 
## Developer Notes:
###
#  
#  
##
## This script reads a list of designs and assoc. subdesigns
## and builds an ordered list for compile

## Sub to create a dependancy list keyed by design
## value is a list of sub-designs directly below the key design
## Requires a fileref to the file containing
## a csv list of design, sub1, sub2,...,subn
## returns a count of lines processed
##--------------------------------------------------------------
sub create_subs {
  my $subref = shift;
  my $fileref = shift;

  my $cnt = 0;
  while(<$fileref>) {
    next if /^\s*#/; ## ignore comments
    s/#.*$//; ## chop of end of line comments
    chomp;
    my @data = split /\s*\,\s*/, $_;
    ## Design should be $data[0], subdesigns $data[1..n];
    my $design = shift @data;
    @{$subref->{$design}} = @data;
    $cnt++;
  }
  return $cnt;
}

##--------------------------------------------------------------
## sub to figure out the top-most (one only) design in the subs list
## requires a ref to the subs list
## returns a design name
sub figure_top {
  my $subref = shift;
  my %parents;
  foreach ( keys %$subref ) {
    $parents{$_}++;
  }
  ##print STDERR "Debug: Parents = ", join(':', keys %parents),"\n";
  my $tmp;
  foreach $tmp ( keys %$subref ) {
    foreach ( @{$subref->{$tmp}} ) {
      delete $parents{$_} if defined $parents{$_};
      ##print STDERR "Debug: trashing $_\n";

    }
  } 
  my @top_design = keys %parents;
  ##print STDERR "Debug: Parents = $top_design[0]\n";
  return $top_design[0];
}
  
##--------------------------------------------------------------
sub create_depths {
  my $design = shift;
  my $subsref = shift;
  my $depthref = shift;
  ##print STDERR "Debug: depth on $design\n";

  $depthref->{$design} = 1 unless defined $depthref->{$design};
  my $current_depth = $depthref->{$design};
  my $lower_depth = 0;
  foreach ( @{$subsref->{$design}} ) {
    $depthref->{$_} = $current_depth + 1;
    my $tdepth = create_depths( $_, $subsref, $depthref);
    $lower_depth = $tdepth if $tdepth > $lower_depth; 
  }
  return ($lower_depth > $current_depth ) ? $lower_depth : $current_depth;
}


##--------------------------------------------------------------
## This sub returns a NEGATIVE integer denoting how far down
## a design is in the design hierarchy
sub depth_of {
  my $design = shift;
  my $subsref = shift;
  ##print STDERR "Debug: Calling depth_of $design\n";

  return -1 unless defined ${$subsref->{$design}}[0];

  my $max_depth = 0;
  foreach (@{$subsref->{$design}}) {
    ##print STDERR "Debug: Checking subdesign $_\n";
    my $tdepth = depth_of($_, $subsref);
    $max_depth = $tdepth if $tdepth < $max_depth;
  }

  return $max_depth - 1;
}

##--------------------------------------------------------------
## sub to return an array of children of given design
## optionally return all procreations of this design (down the hierarchy)
sub children_of {
  my $design = shift;
  my $all = shift;
  my $subsref = shift;
  my @kids = @{$subsref->{$design}};
  ##print STDERR "Debug: $design spawned ", join( ',', @kids), "\n";
  if( $all ) {
    ##print STDERR "Debug: going for all of $design\n";
    foreach (@{$$subsref{$design}}) {
      push @kids, children_of($_, $all, $subsref);
    }
  }
  return @kids; 
}

##--------------------------------------------------------------
sub dump_makefile {
  my $subsref = shift;
  my $depthsref = shift;
  my $top_design = shift;
  my $makeinc = shift;
  my $depth = shift;
  my $makefile = shift;
  my $fileref = shift;

  ## print STDERR "Debug: dumping makefile to level $dept\n";
  my $makertl = $makefile . ".RTL";
  my $makegate = $makefile . ".GATES";
  my $makelocal = $makefile . ".LOCAL";

  print $fileref <<"EOMAKEHEAD";
##
## This file was auto-generated 
## by AFETC Generated Script - Edit with care
##
## All edits here may be overwritten
## Edit the include file to setup design and system parameters to keep
## I promise to honor them

usage ::
	echo "Usage of this Makefile"; \\
   echo "  This Makefile is automaticly generated with the AFETC tool."; \\
   echo "    The AFETC tool expects the user to have created a "; \\
   echo "    <module>.designlist from the GTECH database using the ??? funciton." ; \\
   echo "    A simple <module>.designlist is shown below.  With this example a user "; \\
   echo "    could use the AFETC tool to generate a template for generating "; \\
   echo "    the GTECH design which includes the call to the ??? function. "; \\
   echo "  Once the user has the <module>.designlist file the AFETC tool is "; \\
   echo "  used to generate all the supporting scripts and this Makefile."; \\
   echo " "; \\
   echo "  The user is expected to supply a top level timing constraint file written "; \\
   echo "  in the dc-Tcl language which is compatible with Prime Time. The filename is "; \\
   echo "  <module>.con and should be located in the syn directory.";

## set the default to Bourne Shell
SHELL = /bin/sh

include $makeinc

## Now to do some checks for directories and stuff
\${RTLPATH} ::
	echo "Information: Checking for directory \$@";
	if [ ! -d \$\@ ]; then mkdir \$\@; fi

\${GDBPATH}.0 ::
	echo "Information: Checking for directory \$@";
	if [ ! -d \$\@ ]; then mkdir \$\@; fi

\${GDBPATH} ::
	echo "Information: Checking for directory \$@";
	if [ ! -d \$\@ ]; then mkdir \$\@; fi

\${DBPATH}.0 ::
	echo "Information: Checking for directory \$@";
	if [ ! -d \$\@ ]; then mkdir \$\@; fi

\${DBPATH}.1 ::
	echo "Information: Checking for directory \$@";
	if [ ! -d \$\@ ]; then mkdir \$\@; fi

\${DBPATH}.2 ::
	echo "Information: Checking for directory \$@";
	if [ ! -d \$\@ ]; then mkdir \$\@; fi

# if more than two passes are necessary setup those directories.
\${DBPATH}.\${PASS} ::
	echo "Information: Checking for directory \$@";
	if [ ! -d \$\@ ]; then mkdir \$\@; fi

\${REPSPATH} ::
	echo "Information: Checking for directory \$@";
	if [ ! -d \$\@ ]; then mkdir \$\@; fi

\${CONSPATH} ::
	echo "Information: Checking for directory \$@";
	if [ ! -d \$\@ ]; then mkdir \$\@; fi
	cd \$\@; ln -s ../\${TOP_DESIGN}.\${TCONEXT} .; cd ..

\${LOGSPATH} ::
	echo "Information: Checking for directory \$@";
	if [ ! -d \$\@ ]; then mkdir \$\@; fi

\${LAYOUTPATH} ::
	echo "Information: Checking for directory \$@";
	if [ ! -d \$\@ ]; then mkdir \$\@; fi

\${FLOORPLANPATH} ::
	echo "Information: Checking for directory \$@";
	if [ ! -d \$\@ ]; then mkdir \$\@; fi

tmp ::
	echo "Information: Checking for directory \$@";
	if [ ! -d \$\@ ]; then mkdir \$\@; fi

## This is a simple rule to get the search_path
## and link_path to db_shell
vlsidiv_dct.setup :: vlsidiv_dc.setup
	\${DCTXSCRIPT} \$< \$@; mv \$@ tmp/\$(\@F).tdct; sed "s/^echo/#echo/" tmp/\$(\@F).tdct > \$@;

## simple rule to ensure that the constraints are modified
##  to something that works for DCT
\${CONSPATH}/%.\${TCONEXT} :: \${CONSPATH}/%.\${CONEXT}
	\${DCTXSCRIPT} \$< \$\@; mv \$\@ tmp/\$(\@F).tdct; sed "s/^echo/#echo/" tmp/\$(\@F).tdct > \$\@; rm tmp/\$(\@F).tdct

## Default rule for uncompressing files:
% :: %.gz
	/apps/bin/gunzip \$<
   

.INIT :: tmp \\
    \${LOGSPATH} \\
    \${LAYOUTPATH} \\
    \${FLOORPLANPATH} \\
    \${CONSPATH} \${REPSPATH} \\
    \${DBPATH}.0 \${DBPATH}.1 \${DBPATH}.2 \\
    \${GDBPATH}.0 \\
    \${GDBPATH} \\
    \${INITCONS} \${DCTSCR} \${DBSCR} vlsidiv_dct.setup \\
    \${TOP_DESIGN}.\${TCONEXT} 

setup :: .INIT

clean_gtech ::
	rm \${LOGSPATH}/\*gtech* \\
    \${REPSPATH}/\*_gtech* \\
    \${GDBPATH}.0/\*.\${GDBEXT} \\
    \${GDBPATH}/\*.\${GDBEXT};

clean ::
	rm \${LOGSPATH}/\* \\
	\${REPSPATH}/\* \\
	\${CONSPATH}/\*.[0-9]*.\${CONEXT} \\
	\${CONSPATH}/\*.[0-9]*.\${TCONEXT} \\
	\${CONSPATH}/\*.[0-9]*.\${CONEXT}.chk \\
	\${DBPATH}.0/\*.\${DBEXT} \\
	\${DBPATH}.1/\*.\${DBEXT} \\
	\${DBPATH}.2/\*.\${DBEXT};

really_clean ::
	rm -f gth_global.dct gth_generic.dct \${TOP_DESIGN}.ordered.tcl gt_global.dct  dc_global.dct \\
    dch_global.dct \${TOP_DESIGN}.initial.dct db_global.dct generic_layout.dct generic_fp.dct generic_pt.dct \\
    generic_area.dct generic_tc.dct generic_compile.scr generic_hier_compile.scr generic_wireload.tcl generic_buildwl.dct \\
    generic_chip.dct generic_fpm.dct README.afetc vlsidiv_dct.setup ;
	rm -rf tcl tmp;
	rm -rf \${DBPATH}.0 \\
    \${REPSPATH} \\
    \${CONSPATH} \\
    \${GDBPATH}.0 \\
    \${GDBPATH} \\
    \${DBPATH}.1 \\
    \${DBPATH}.2 ;
	rm Makefile Makefile.RTL Makefile.GATES;

compress_logs ::
	echo "Information: Compressing Pass=\${PASS} log files...";
	cd \${LOGSPATH}; /apps/bin/gzip \*.gtech.log; /apps/bin/gzip \*.\${PASS}.log

# now build a handy minus one operator.
PASS_MINUS_ONE := \$(shell expr \${PASS} - 1)
PASS_MINUS_TWO := \$(shell expr \${PASS} - 2)
PASS_PLUS_ONE := \$(shell expr \${PASS} + 1)

## Now for the serious stuff
all_hier_gtech :: \${GDBPATH}/\${TOP_DESIGN}_hier.\${GDBEXT}

all_gtech :: \${GDBPATH}.0/\${TOP_DESIGN}.\${GDBEXT}

all_hier :: \${DBPATH}.\${PASS}/\${TOP_DESIGN}_hier.\${DBEXT}

all :: \${DBPATH}.\${PASS}/\${TOP_DESIGN}.\${DBEXT}

chip :: \${DBPATH}.\${PASS}/\${CHIP_DESIGN}.\${DBEXT}

scan_chip :: \${DBPATH}.\${PASS}/\${CHIP_DESIGN}_scan.\${DBEXT}

2layout :: \${LAYOUTPATH}/files.\${PASS}/\${CHIP_DESIGN}.\${VLOGEXT}

2fp :: \${FLOORPLANPATH}/files.\${PASS}/\${CHIP_DESIGN}.\${VLOGEXT}

scan :: \${DBPATH}.\${PASS}/\${TOP_DESIGN}_scan.\${DBEXT}

my_library :: \${DBPATH}.\${PASS}/my_\${FOUNDRY_LIB}.\${DBEXT}

pre2postgate :: formal_gate_vs_layout.\${PASS}

## Top design for GTECH
\${GDBPATH}/\${TOP_DESIGN}_hier.\${GDBEXT} :: \${DCGSCR} \${GDBPATH}.0/\${TOP_DESIGN}.\${GDBEXT}
	\${DCTSH} -x "set TDT_des  \${TOP_DESIGN};\\
      set TDT_gtech_hier \${GTECHIER};\\
      set TDT_gdbdir \${GDBPATH};set TDT_gdbext \${GDBEXT};\\
      set TDT_repdir \${REPSPATH};"\\
      -f \${GTHSCR} | tee \${LOGSPATH}/\${TOP_DESIGN}_gtech_hier.\${LOGEXT}

## Top design for budgeting
\${DBPATH}.\${PASS}/\${TOP_DESIGN}_hier.\${DBEXT} :: \${DBPATH}.\${PASS}/\${TOP_DESIGN}.\${DBEXT} \${DCHSCR}
	\${DCTSH} -x "set TDT_des  \${TOP_DESIGN};\\
      set TDT_dont_use_cells \${XCELL};\\
      set TDT_fpdir \${FLOORPLANPATH};\\
      set TDT_custom_wireload \${WIRELOADS};\\
      set TDT_foundry_lib \${FOUNDRY_LIB};\\
      set TDT_pass \${PASS};set TDT_consdir \${CONSPATH};\\
      set TDT_dbdir \${DBPATH};set TDT_dbext \${DBEXT};\\
      set TDT_gdbdir \${GDBPATH};set TDT_gdbext \${GDBEXT};\\
      set TDT_repdir \${REPSPATH};set TDT_conext \${TCONEXT};"\\
      -f \${DCHSCR} | tee \${LOGSPATH}/\${TOP_DESIGN}_hier.\${PASS}.\${LOGEXT}

## Build the custom library with wireloads
\${DBPATH}.\${PASS}/my_\${FOUNDRY_LIB}.\${DBEXT} :: \${GDBPATH}/\${TOP_DESIGN}_hier.\${GDBEXT} \${WLSCR}
	\${DCTSH} -x "set TDT_fpdir \${FLOORPLANPATH};\\
      set TDT_custom_wireload \${WIRELOADS};\\
      set TDT_foundry_lib \${FOUNDRY_LIB};\\
      set TDT_pass \${PASS};\\
      set TDT_dbdir \${DBPATH}; set TDT_dbext \${DBEXT}; read_db \$<; link;"\\
      -f \${WLSCR} | tee \${LOGSPATH}/my_\${FOUNDRY_LIB}.\${PASS}.\${LOGEXT}


## Top Level Timing Report
timing.\${PASS} :: \${DBPATH}.\${PASS}/\${TOP_DESIGN}_hier.\${DBEXT}
	\${DCTSH} -x "set TDT_des  \${TOP_DESIGN};\\
      set TDT_pass \${PASS};set TDT_consdir \${CONSPATH};\\
      set TDT_dbdir \${DBPATH};set TDT_dbext \${DBEXT};\\
      set TDT_repdir \${REPSPATH};set TDT_conext \${TCONEXT}; read_db \$<;\\
      redirect [format "%s%s"  [format "%s%s"  [format "%s%s" [format "%s%s" \${REPSPATH} {/}] \${TOP_DESIGN}] {.\${PASS}}] {.tim.rpt}] { report_timing -max_path \${TIMINGPATHS} -nworst 10 -path full -nosplit }; exit; "\\
      | tee \${LOGSPATH}/\${TOP_DESIGN}_timing.\${PASS}.\${LOGEXT} && touch timing.\${PASS}


##
## Setup of Chip Specific Data; each chip is different which is why we have this section here
##
\${DBPATH}.\${PASS}/\${CHIP_DESIGN}.\${DBEXT} :: \${DBPATH}.\${PASS}/\${TOP_DESIGN}_hier.\${DBEXT} \${RTLPATH}/\${CHIP_DESIGN}.v
	\${DCTSH} -x "set TDT_des  \${CHIP_DESIGN};\\
      set TDT_top \$<;\\
      set TDT_dont_use_cells \${XCELL};\\
      set TDT_rtl \${RTLPATH};\\
      set TDT_fpdir \${FLOORPLANPATH};\\
      set TDT_custom_wireload \${WIRELOADS};\\
      set TDT_foundry_lib \${FOUNDRY_LIB};\\
      set TDT_pass \${PASS};set TDT_consdir \${CONSPATH};\\
      set TDT_dbdir \${DBPATH};set TDT_dbext \${DBEXT};\\
      set TDT_repdir \${REPSPATH};set TDT_conext \${TCONEXT};"\\
      -f \${DCCSCR} | tee \${LOGSPATH}/\${CHIP_DESIGN}.\${PASS}.\${LOGEXT}


## Scan based chip
\${DBPATH}.\${PASS}/\${CHIP_DESIGN}_scan.\${DBEXT} :: \${DBPATH}.\${PASS}/\${TOP_DESIGN}_scan.\${DBEXT} \${RTLPATH}/\${CHIP_DESIGN}.v
	\${DCTSH} -x "set TDT_des  \${CHIP_DESIGN};\\
      set TDT_top \$<;\\
      set TDT_dont_use_cells \${XCELL};\\
      set TDT_rtl \${RTLPATH};\\
      set TDT_fpdir \${FLOORPLANPATH};\\
      set TDT_custom_wireload \${WIRELOADS};\\
      set TDT_foundry_lib \${FOUNDRY_LIB};\\
      set TDT_pass \${PASS};set TDT_consdir \${CONSPATH};\\
      set TDT_dbdir \${DBPATH};set TDT_dbext \${DBEXT};\\
      set TDT_repdir \${REPSPATH};set TDT_conext \${TCONEXT};"\\
      -f \${DCCSCR} | tee \${LOGSPATH}/\${CHIP_DESIGN}.\${PASS}.\${LOGEXT}
	echo "Information: Linking Chip to Scan_Chip";
	if [ -r \${DBPATH}.\${PASS}/\${CHIP_DESIGN}_scan.\${DBEXT} ]; then rm \${DBPATH}.\${PASS}/\${CHIP_DESIGN}_scan.\${DBEXT}; fi
	cd \${DBPATH}.\${PASS}; ln -s \${CHIP_DESIGN}.\${DBEXT} \${CHIP_DESIGN}_scan.\${DBEXT};

## Scan based chip
\${DBPATH}.\${PASS}/\${CHIP_DESIGN}_test.\${DBEXT} :: \${DBPATH}.\${PASS}/\${CHIP_DESIGN}_scan.\${DBEXT}
	\${DCTSH} -x "set TDT_des  \${CHIP_DESIGN};\\
      set TDT_dont_use_cells \${XCELL};\\
      set TDT_rtl \${RTLPATH};\\
      set TDT_fpdir \${FLOORPLANPATH};\\
      set TDT_custom_wireload \${WIRELOADS};\\
      set TDT_foundry_lib \${FOUNDRY_LIB};\\
      set TDT_pass \${PASS};set TDT_consdir \${CONSPATH};\\
      set TDT_dbdir \${DBPATH};set TDT_dbext \${DBEXT};\\
      set TDT_repdir \${REPSPATH};set TDT_conext \${TCONEXT}; read_db \$<;"\\
      -f \${TESTSCR} | tee \${LOGSPATH}/\${CHIP_DESIGN}_test.\${PASS}.\${LOGEXT}


## Chip Level Timing Report
chip_timing.\${PASS} :: \${DBPATH}.\${PASS}/\${CHIP_DESIGN}.\${DBEXT}
	\${DCTSH} -x "set TDT_des  \${CHIP_DESIGN};\\
      set TDT_pass \${PASS};set TDT_consdir \${CONSPATH};\\
      set TDT_dbdir \${DBPATH};set TDT_dbext \${DBEXT};\\
      set TDT_repdir \${REPSPATH};set TDT_conext \${TCONEXT}; read_db \$<;\\
      redirect [format "%s%s"  [format "%s%s"  [format "%s%s" [format "%s%s" \${REPSPATH} {/}] \${CHIP_DESIGN}] {.\${PASS}}] {.tim.rpt}] { report_timing -max_path \${TIMINGPATHS} -nworst 10 -path full -nosplit }; exit; "\\
      | tee \${LOGSPATH}/\${CHIP_DESIGN}_timing.\${PASS}.\${LOGEXT} && touch chip_timing.\${PASS}


## Chip level area and power
area.\${PASS} :: \${DBPATH}.\${PASS}/\${CHIP_DESIGN}.\${DBEXT} \${APSCR}
	\${DCTSH} -x "set TDT_des  \${CHIP_DESIGN};\\
      set TDT_pass \${PASS};set TDT_consdir \${CONSPATH};\\
      set TDT_dbdir \${DBPATH};set TDT_dbext \${DBEXT};\\
      set TDT_repdir \${REPSPATH};set TDT_conext \${TCONEXT};"\\
    -f \${APSCR} | tee \${LOGSPATH}/\${CHIP_DESIGN}_area.\${PASS}.\${LOGEXT} && touch area.\${PASS}

## Chip Level Test Compiler Run
\${DBPATH}.\${PASS}/\${TOP_DESIGN}_scan.\${DBEXT} :: \${DBPATH}.\${PASS_MINUS_ONE}/\${TOP_DESIGN}_hier.\${DBEXT} \${TCSCR}
	\${DCTSH} -x "set TDT_des  \${TOP_DESIGN};\\
      set TDT_pass \${PASS};set TDT_consdir \${CONSPATH};\\
      set TDT_dont_use_cells \${XCELL};\\
      set TDT_dbdir \${DBPATH};set TDT_dbext \${DBEXT};\\
      set TDT_repdir \${REPSPATH};set TDT_conext \${TCONEXT};"\\
    -f \${TCSCR} | tee \${LOGSPATH}/\${TOP_DESIGN}.\${PASS}.\${LOGEXT} && touch scan.\${PASS}

## Write out the Verilog for the chip design.
\${CHIP_DESIGN}_gates.\${PASS}.v :: \${DBPATH}.\${PASS}/\${CHIP_DESIGN}.\${DBEXT}
	\${DCTSH} -x "set TDT_des  \${CHIP_DESIGN};\\
      set TDT_pass \${PASS};set TDT_consdir \${CONSPATH};\\
      set TDT_dbdir \${DBPATH};set TDT_dbext \${DBEXT};\\
      set TDT_repdir \${REPSPATH};set TDT_conext \${TCONEXT};\\
      read_db \$<; write -hierarchy -format verilog -output \$@ ; exit" | tee \${LOGSPATH}/\${CHIP_DESIGN}_gates.\${PASS}.\${LOGEXT}


## All of these funcitons are post runs so the source directories are called "in"
## Chip Level PrimeTime Run from Layout information.
pt_layout.\${PASS} :: \${LAYOUTPATH}/files_in.\${PASS}/\${CHIP_DESIGN}.\${VLOGEXT} \${LAYOUTPATH}/files_in.\${PASS}/\${CHIP_DESIGN}.sdf \${PTSCR}
	\${PTSH} -x "set TDT_des  \${CHIP_DESIGN};\\
      set TDT_srcfile \$(<F);\\
      set TDT_postlayout {true};\\
      set TDT_pass \${PASS};set TDT_consdir \${CONSPATH};\\
      set TDT_sdfdir \${LAYOUTPATH}/files_in.\${PASS}; set TDT_sdfext sdf;\\
      set TDT_dbdir \${LAYOUTPATH}/files_in.\${PASS}; set TDT_dbext \${DBEXT};\\
      set TDT_repprefix .pt_layout.;\\
      set TDT_repdir \${REPSPATH};set TDT_conext \${TCONEXT};"\\
    -f \${PTSCR} | tee \${LOGSPATH}/\${CHIP_DESIGN}_pt_layout.\${PASS}.\${LOGEXT} && touch pt_layout.\${PASS}

##
## DC Layout creates a hierarchical db used for the PrimeTime based budget to operate on.
dc_layout.\${PASS} :: \${LAYOUTPATH}/files_in.\${PASS}/\${CHIP_DESIGN}.\${VLOGEXT} \${LAYOUTPATH}/files_in.\${PASS}/\${CHIP_DESIGN}.sdf \${PTSCR}
	\${PTSH} -x "set TDT_des  \${CHIP_DESIGN};\\
      set TDT_srcfile \$(<F);\\
      set TDT_postlayout {true};\\
      set TDT_pass \${PASS};set TDT_consdir \${CONSPATH};\\
      set TDT_sdfdir \${LAYOUTPATH}/files_in.\${PASS}; set TDT_sdfext sdf;\\
      set TDT_dbdir \${LAYOUTPATH}/files_in.\${PASS}; set TDT_dbext \${DBEXT};\\
      set TDT_repprefix .pt_layout.;\\
      set TDT_repdir \${REPSPATH};set TDT_conext \${TCONEXT};"\\
    -f \${PTSCR} | tee \${LOGSPATH}/\${CHIP_DESIGN}_pt_layout.\${PASS}.\${LOGEXT} && touch pt_layout.\${PASS}

##
## Use PrimeTime to create a new budget of the design.
budget_layout.\${PASS} :: \${LAYOUTPATH}/files_in.\${PASS}/\${CHIP_DESIGN}.\${VLOGEXT} \${LAYOUTPATH}/files_in.\${PASS}/\${CHIP_DESIGN}.sdf \${PTBSCR}
	\${PTSH} -x "set TDT_des  \${CHIP_DESIGN};\\
      set TDT_srcfile \$(<F);\\
      set TDT_postlayout {true};\\
      set TDT_pass \${PASS};set TDT_consdir \${CONSPATH};\\
      set TDT_sdfdir \${LAYOUTPATH}/files_in.\${PASS}; set TDT_sdfext sdf;\\
      set TDT_dbdir \${LAYOUTPATH}/files_in.\${PASS}; set TDT_dbext \${DBEXT};\\
      set TDT_repprefix .pt_layout_budget.;\\
      set TDT_repdir \${REPSPATH};set TDT_conext \${TCONEXT};"\\
    -f \${PTBSCR} | tee \${LOGSPATH}/\${CHIP_DESIGN}_pt_layout_budget.\${PASS}.\${LOGEXT} && touch pt_layout.\${PASS}

## Chip Level Floorplan manager from the layout information.
\${LAYOUTPATH}/files_in.\${PASS}/\${CHIP_DESIGN}.\${TCONEXT} :: \${LAYOUTPATH}/files_in.\${PASS}/\${CHIP_DESIGN}.dc
	\${DCTXSCRIPT} \$< \$@; mv \$@ tmp/\$(\@F).tdct; sed "s/^echo/#echo/" tmp/\$(\@F).tdct > \$@;

fpm_layout.\${PASS} :: \${LAYOUTPATH}/files_in.\${PASS}/\${CHIP_DESIGN}.\${VLOGEXT} \${LAYOUTPATH}/files_in.\${PASS}/\${CHIP_DESIGN}.\${TCONEXT} \${LAYOUTPATH}/files_in.\${PASS}/\${CHIP_DESIGN}.pdef \${LAYOUTPATH}/files_in.\${PASS}/\${CHIP_DESIGN}.sdf \${FPMSCR}
	\${DCTSH} -x "set TDT_des  \${CHIP_DESIGN};\\
      set TDT_srcfile \$<;\\
      set TDT_postlayout {true};\\
      set TDT_pass \${PASS};set TDT_consdir \${CONSPATH};\\
      set TDT_phydir \${LAYOUTPATH}/files_in.\${PASS};\\
      set TDT_sdfext sdf; set TDT_pdefext pdef;\\
      set TDT_dont_use_cells \${XCELL};\\
      set TDT_hierarchy \${CHIP_HIERARCHY};\\
      set TDT_dbdir \${DBPATH};set TDT_dbext \${DBEXT};\\
      set TDT_repprefix .fpm_layout.;\\
      set TDT_repdir \${REPSPATH};set TDT_conext \${TCONEXT};"\\
    -f \${FPMSCR} | tee \${LOGSPATH}/\${CHIP_DESIGN}_fpm_layout.\${PASS}.\${LOGEXT} && touch fpm_layout.\${PASS}
	echo "Information: Building Placeholder for Layout Returned Files";
	if [ ! -d \${LAYOUTPATH}/files.\${PASS_PLUS_ONE} ]; then mkdir \${LAYOUTPATH}/files.\${PASS_PLUS_ONE} ; fi
	if [ -r \${LAYOUTPATH}/files_in.\${PASS_PLUS_ONE} ]; then rm \${LAYOUTPATH}/files_in.\${PASS_PLUS_ONE} ; fi
	cd \${LAYOUTPATH}; ln -s files.\${PASS_PLUS_ONE} files_in.\${PASS_PLUS_ONE};
	cd \${LAYOUTPATH}/files.\${PASS}; for i in `ls *.timing.rpt`; do mv \$\$i \$\$i.orig; sed 's#1999.10#1999.05-2#' \$\$i.orig > \$\$i; done

formal_gate_vs_layout.\${PASS} :: \${LAYOUTPATH}/files_in.\${PASS}/\${CHIP_DESIGN}.\${VLOGEXT} \${DBPATH}.\${PASS_MINUS_TWO}/\${CHIP_DESIGN}.\${DBEXT} \${FMSCR}
	\${FMSH} -x "set TDT_des  \${CHIP_DESIGN};\\
      set TDT_srcfile \$<;\\
      set TDT_pass \${PASS};set TDT_consdir \${CONSPATH};\\
      set TDT_phydir \${LAYOUTPATH}/files_in.\${PASS};\\
      set TDT_dbdir \${DBPATH};set TDT_dbext \${DBEXT};\\
      set TDT_repprefix .fm_layout.;\\
      set TDT_repdir \${REPSPATH};set TDT_conext \${TCONEXT};"\\
    -f \${FMSCR} | tee \${LOGSPATH}/\${CHIP_DESIGN}_fm_layout.\${PASS}.\${LOGEXT} && touch fm_layout.\${PASS}

## Chip Level PrimeTime Run from Floorplan information.
pt_fp.\${PASS} :: \${LAYOUTPATH}/files_in.\${PASS}/\${CHIP_DESIGN}.\${VLOGEXT} \${LAYOUTPATH}/files_in.\${PASS}/\${CHIP_DESIGN}.sdf \${PTSCR}
	\${PTSH} -x "set TDT_des  \${CHIP_DESIGN};\\
      set TDT_srcfile \$(<F);\\
      set TDT_postlayout {false};\\
      set TDT_pass \${PASS};set TDT_consdir \${CONSPATH};\\
      set TDT_sdfdir \${LAYOUTPATH}/files_in.\${PASS}; set TDT_sdfext sdf;\\
      set TDT_dbdir \${LAYOUTPATH}/files_in.\${PASS}; set TDT_dbext \${DBEXT};\\
      set TDT_repprefix .pt_fp.;\\
      set TDT_repdir \${REPSPATH};set TDT_conext \${TCONEXT};"\\
    -f \${PTSCR} | tee \${LOGSPATH}/\${CHIP_DESIGN}_pt_fp.\${PASS}.\${LOGEXT} && touch pt_fp.\${PASS}

## Chip Level Floorplan manager from the floorplan information.

fpm_fp.\${PASS} :: \${LAYOUTPATH}/files_in.\${PASS}/\${CHIP_DESIGN}.\${VLOGEXT} \${LAYOUTPATH}/files_in.\${PASS}/\${CHIP_DESIGN}.\${TCONEXT} \${LAYOUTPATH}/files_in.\${PASS}/\${CHIP_DESIGN}.pdef \${LAYOUTPATH}/files_in.\${PASS}/\${CHIP_DESIGN}.sdf \${PREFPMSCR}
	\${DCTSH} -x "set TDT_des  \${CHIP_DESIGN};\\
      set TDT_srcfile \$<;\\
      set TDT_postlayout {false};\\
      set TDT_pass \${PASS};set TDT_consdir \${CONSPATH};\\
      set TDT_phydir \${LAYOUTPATH}/files_in.\${PASS};\\
      set TDT_wldir \${LAYOUTPATH}/files.\${PASS_MINUS_ONE};\\
      set TDT_foundry_lib \${FOUNDRY_LIB};\\
      set TDT_custom_wireload \${WIRELOADS};\\
      set TDT_sdfext sdf; set TDT_pdefext pdef;\\
      set TDT_dont_use_cells \${XCELL};\\
      set TDT_hierarchy \${CHIP_HIERARCHY};\\
      set TDT_dbdir \${DBPATH};set TDT_dbext \${DBEXT};\\
      set TDT_repprefix .fpm_fp.;\\
      set TDT_repdir \${REPSPATH};set TDT_conext \${TCONEXT};"\\
    -f \${PREFPMSCR} | tee \${LOGSPATH}/\${CHIP_DESIGN}_fpm_fp.\${PASS}.\${LOGEXT} && touch fpm_fp.\${PASS}
	echo "Information: Building Placeholder for Layout Returned Files";
	if [ ! -d \${LAYOUTPATH}/files.\${PASS_PLUS_ONE} ]; then mkdir \${LAYOUTPATH}/files.\${PASS_PLUS_ONE} ; fi
	if [ -r \${LAYOUTPATH}/files_in.\${PASS_PLUS_ONE} ]; then rm \${LAYOUTPATH}/files_in.\${PASS_PLUS_ONE} ; fi
	cd \${LAYOUTPATH}; ln -s files.\${PASS_PLUS_ONE} files_in.\${PASS_PLUS_ONE};
	cd \${LAYOUTPATH}/files.\${PASS}; for i in `ls *.timing.rpt`; do mv \$i \$i.orig; sed 's#1999.10#1999.05-2#' \$i.orig > \$i; done

## *** This operation done to the layout directory
## Write out the Verilog for the top of the design.
## since comments are not allowed in these stream files here is what we are doing:
## # 1. read in the database 
## # 2. Call script
## # 3. Build the placeholder for the returned data
## # 4. 
\${LAYOUTPATH}/files.\${PASS}/\${CHIP_DESIGN}.v :: \${DBPATH}.\${PASS}/\${CHIP_DESIGN}_scan.\${DBEXT}
	\${DCTSH} -x "set TDT_des  \${CHIP_DESIGN};\\
      set TDT_pass \${PASS};set TDT_consdir \${CONSPATH};\\
      set TDT_dbdir \${DBPATH};set TDT_dbext \${DBEXT};\\
      set TDT_repdir \${REPSPATH};set TDT_conext \${TCONEXT};\\
      set TDT_layoutdir \${LAYOUTPATH}/files.\${PASS};\\
      set TDT_hierarchy \${CHIP_HIERARCHY};\\
      read_db \$<; " \\
      -f \${LAYOUTSCR}  | tee \${LOGSPATH}/\${CHIP_DESIGN}_tolayout.\${PASS}.\${LOGEXT};
	echo "Information: Building Placeholder for Layout Returned Files";
	if [ ! -d \${LAYOUTPATH}/files.\${PASS_PLUS_ONE} ]; then mkdir \${LAYOUTPATH}/files.\${PASS_PLUS_ONE} ; fi
	if [ -r \${LAYOUTPATH}/files_in.\${PASS_PLUS_ONE} ]; then rm \${LAYOUTPATH}/files_in.\${PASS_PLUS_ONE} ; fi
	cd \${LAYOUTPATH}; ln -s files.\${PASS_PLUS_ONE} files_in.\${PASS_PLUS_ONE};
	cd \${LAYOUTPATH}/files.\${PASS}; for i in `ls *.timing.rpt`; do mv \$i \$i.orig; sed 's#1999.10#1999.05-2#' \$i.orig > \$i; done

## *** This operation done to the floorplan director ***
## Write out the Verilog for the top of the design.
## since comments are not allowed in these stream files here is what we are doing:
## # 1. read in the database 
## # 6. run a script
\${FLOORPLANPATH}/files.\${PASS}/\${CHIP_DESIGN}.v :: \${DBPATH}.\${PASS}/\${CHIP_DESIGN}.\${DBEXT}
	\${DCTSH} -x "set TDT_des  \${CHIP_DESIGN};\\
      set TDT_pass \${PASS};set TDT_consdir \${CONSPATH};\\
      set TDT_dbdir \${DBPATH};set TDT_dbext \${DBEXT};\\
      set TDT_repdir \${REPSPATH};set TDT_conext \${TCONEXT};\\
      set TDT_fpdir \${FLOORPLANPATH}/files.\${PASS};\\
      set TDT_hierarchy \${CHIP_HIERARCHY};\\
      read_db \$<; "\\
      -f \${FPSCR} | tee \${LOGSPATH}/\${CHIP_DESIGN}_2fp.\${PASS}.\${LOGEXT}

#
## End of Chip Specific Stuff; beginning of the real make and budget engine on a bottom up basis.
#

## Budget design
budgets.\${PASS} :: \${DBPATH}.\${PASS}/\${TOP_DESIGN}_hier.\${DBEXT} .synopsys_pt.setup
	\${DBSH} -f \${DBSCR} -x "\\
      set TDT_dbdir \${DBPATH};\\
      set TDT_pass \${PASS}; \\
      set TDT_custom_wireload \${WIRELOADS};\\
      set TDT_foundry_lib \${FOUNDRY_LIB};\\
      set TDT_consdir \${CONSPATH}; \\
      set TDT_consext \${CONEXT}; \\
      set TDT_top_constraints \${CONSPATH}/\${TOP_DESIGN}.\${TCONEXT}; \\
      set TDT_level $depth; \\
      set TDT_file \$(<F);" | tee \${LOGSPATH}/allocate_budget.\${PASS}.\${LOGEXT} && touch budgets.\${PASS}

## Now to make the actual designs

# they are included to give us some granularity in the design.

include $makertl
include $makegate
include $makelocal

EOMAKEHEAD
print $fileref "\n## end of ", $makefile, "\n";

}

##--------------------------------------------------------------
## This section has all the GTECH script included in it so that it is 
##  easy to isolate.
##--------------------------------------------------------------
sub dump_rtl_makefile {
  my $subsref = shift;
  my $depthsref = shift;
  my $top_design = shift;
  my $makeinc = shift;
  my $depth = shift;
  my $fileref = shift;

  ## print STDERR "Debug: dumping makefile to level $depth\n";

  print $fileref <<"EOMAKERTLHEAD";
##
## This file was auto-generated 
## by build_verilog_make.pl Generated Script - Edit with care
##
## All edits here may be overwritten
## Edit the include file to setup design and system parameters to keep
## I promise to honor them

## Now to make the actual designs
EOMAKERTLHEAD

  foreach( keys %$subsref ) {
    chomp;
    my $cdepth = $depthsref->{$_};
    my @subs = ();

    ##print $fileref "##" if $cdepth > $depth; 
    ## don't provide target for blocks below target depth
    if ($cdepth > $depth) {  # we want to not make the lower level blocks
        print $fileref "## \${GDBPATH}.0/$_.\${GDBEXT} : \${RTLPATH}/$_.\${VLOGEXT} not made\n";
        next; # no need to proceed as there is no support information.
    } else {
        print $fileref "\${GDBPATH}.0/$_.\${GDBEXT} : \${RTLPATH}/$_.\${VLOGEXT}";
    }

    if (defined ${$$subsref{$_}}[0]) {
      my $subdes;
      ##print STDERR "Debug: design $_ $cdepth vs $depth\n";
      my @offspring;
      if( $cdepth < $depth ) {
        @offspring = children_of $_, 0, $subsref;
      } else { 
        @offspring = children_of $_, 1, $subsref;
      }
      foreach $subdes (@offspring) {
        if( $cdepth >= $depth ) { ## down to lowest compile depth
          print $fileref "\\\n   \${RTLPATH}/$subdes.\${VLOGEXT}";
          push @subs,  $subdes;
        } else { ## grab the DB from the search path but must have dependancy.
          print $fileref "\\\n   \${GDBPATH}.0/$subdes.\${GDBEXT}";
          # push @subs,  $subdes;
        }
      }
    }
    print $fileref "\n";
    ##print $fileref "##" if $cdepth > $depth; 
    ## print STDERR "Debug: ", join("\t", @subs), "\n";
    ## don't provide target for blocks below target depth
    print $fileref "\t\${DCTSH} -x \"set TDT_des  $_;\\\n",
      "     set TDT_subs {", join(" ", @subs), "};\\\n",
      "     set TDT_rtldir \${RTLPATH};\\\n",
      "     set TDT_incdir \${INCLUDEPATH};\\\n",
      "     set TDT_vlogext \${VLOGEXT};\\\n",
      "     set TDT_gdbdir \${GDBPATH}.0;set TDT_gdbext \${GDBEXT};\\\n",
      "     set TDT_repdir \${REPSPATH};\"\\\n",
      "     -f \${GTSCR} | tee \${LOGSPATH}/$_.gtech.\${LOGEXT}\n\n";
  }
print $fileref "\n## end of file \n";
}

##--------------------------------------------------------------
sub dump_gt_script {
  my $fileref = shift;

print $fileref <<'EOGTSRC';
# build_verilog_make.pl Generated Script - Edit with care
# generic compile script for
# 
# Creating bottom level GTECH databases from Verilog.
#

if {  $TDT_vlogext == "" } {
   echo {Error: variable TDT_vlogext must be set to the file ext}
  exit 1
}
if {  $TDT_rtldir == "" } {
   echo {Error: variable TDT_rtldir must be set to the directory containing RTL}
  exit 1
}
if {  $TDT_gdbext == "" } {
   echo {Error: variable TDT_gdbext must be set to the GTECH DB file ext}
  exit 1
}
if {  $TDT_gdbdir == "" } {
   echo {Error: variable TDT_gdb must be set to the directory containing GTECH DBs}
  exit 1
}
if {  $TDT_repdir == "" } {
   echo {Warning: TDT_repdir not set, will write reports to cwd}
  set TDT_repdir {.}
}
if {  $TDT_subs == "" } {
   set TDT_subs [list]
}
if {  $TDT_des == "" } {
   echo {Error: design not specified in TDT_des variable}
  exit 1
}

# Modify the search path so that the already optimized childen are found:
set _search_path [format "%s%s"  {./} $TDT_rtldir ]
set search_path [concat  $_search_path $search_path]

# Modify the search path so that the included files are found
set _search_path [format "%s%s"  {./} $TDT_incdir ]
set search_path [concat  $_search_path $search_path]

# Lots of errors will be had if it cannot find the GTECH databases in the search engine but 
#  this is what we want at this level.

###
# These two switches are here to force read_verilog to keep register
#  outputs that we have for SCAN observability that go nowhere.
set dont_munch_design "true"
set dont_clean_design "true"

echo {Info: reading all Verilog subdesigns}
foreach TDT_gdbsub $TDT_subs {
 read_verilog [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_rtldir {/}] $TDT_gdbsub] {.}] $TDT_vlogext]
 }
 
read_verilog [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_rtldir {/}] $TDT_des] {.}] $TDT_vlogext]

set _dc_shell_status [link]
    if { $_dc_shell_status == 0} {
        echo {Info: Expecting Design to NOT Link}
    } else {
        echo {Info: UnExpected Link}
    }

# now write out the design so we have access to it for future stages:
# this is necessary to control where it puts the designs for future reference
foreach_in_collection d [get_designs] {
  current_design $d
  write -format db -output $TDT_gdbdir/$current_design.$TDT_gdbext
}
#
exit
# end of file

EOGTSRC

}
      
##--------------------------------------------------------------
sub dump_outhier_tcl {
  my $fileref = shift;

print $fileref <<'EOOHIER';

# build_verilog_make.pl Generated Script - Edit with care
#  Sample GTECH script that automaticly produces the correct
#  hieararchy design list by using several Procedures.
# 
#
# This is a set of procedures to produce hier 
# DO NOT REMOVE
############################################################ 
#    Property of Storage Technology Corporation
#      
#              Copyright(1999)
#        Storage Technology Corporation
#            All Rights Reserved
#
#    Program name:  OutputHier
#
#    Description: 
#        See individual scripts.
#
#    Author: Walt Strickler               Date: July 16, 1999
#
#    Modified By:
#                                      
############################################################


# OutputHier:  Outputs the hierarchy of all designs in memory to the
#            file FileName in the format requested by Tom Tessier,
#            7/15/99.
#
proc OutputHier {FileName} {
    if [catch { open $FileName w } File] {
        echo "OutputHier: Could not open hierarchy file: $FileName"
    } else {
        puts $File "##"
        
        ParseHier Hier
        
        set DesList [split [array names Hier] " "]
        foreach Des $DesList {
            puts -nonewline $File $Des 

            if {[sizeof_collection $Hier($Des)] == 0} {
                # Do nothing: lowest level
            } else {
                foreach_in_collection Ref $Hier($Des) {
                    puts -nonewline $File ", [Objectify $Ref]"
                    }
                }
            
            puts $File ""    
            puts $File "#"
            }
            
        puts $File "# end of file"
        close $File
        }
    }


# ParseHier:  Takes the name of an array (ArrayName) in the calling scope 
#            and fills this array with the hierarchy under each design
#            in memory.  The array is indexed with the name of each
#            design, and the contents of each element is a collection
#            containing the hierarchical references in the design.
#
proc ParseHier { ArrayName } {
    upvar $ArrayName Hier
    
    set CurrSave [current_design > /dev/null]
        
    foreach_in_collection DesignColl [all_designs] {
        set Design [Objectify $DesignColl]
        current_design $Design > /dev/null
        set Refs [find reference *]

        set HierRefs ""
        foreach_in_collection Ref $Refs {
        if {[get_attribute $Ref "is_hierarchical"] == "true"} {
            set HierRefs [add_to_collection $HierRefs $Ref]
            }
        
        set Hier($Design) $HierRefs
        }
    }
    
    current_design $CurrSave > /dev/null
    }

# Objectify:  Returns a string which is the Ind'th element of Collection Coll
#             Returns "" if Coll is empty
#             Default Ind is 0 (first element)
#
proc Objectify { Coll {Ind 0} } {
    if {[sizeof_collection $Coll] == 0} {
        return ""
        }
        
    set Object [get_attribute [index_collection $Coll $Ind] name]
    return $Object
    }

############################################################ 
#    Property of Storage Technology Corporation
#      
# end of included hierarchy generated source
############################################################ 
EOOHIER
}

##--------------------------------------------------------------
sub dump_gth_script {
  my $fileref = shift;

print $fileref <<'EOGTECH';

# build_verilog_make.pl Generated Script - Edit with care
#  Sample GTECH script that automaticly produces the correct
#  hieararchy design list by using the output_hier.tcl file.
#  
# This is the hierarchy operation file which is responsible for 
#  gathering the total GTECH design together and modifing the
#  hierarchy so that it will better match the capacity of the
#  tools.
#
# This file just reads the database in, links and writes it
#  back out without any changes.
#
# This is a set of procedures to produce hier 
source tcl/output_hier.tcl

# the the design to the top modules
set module $TDT_des

# source a file which contains bottom up compile lists for major blocks
# The file would look like:
# 
source $TDT_gtech_hier

# Modify the search path so that the already GTECHed designs are found:
set _search_path [format "%s%s" [format "%s%s" {./} $TDT_gdbdir ] {.0} ]
set search_path [concat  $_search_path $search_path]

# read the top of the database
read_file [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_gdbdir {.0/}] $TDT_des] {.}] $TDT_gdbext]

# set back to the top
current_design $module
# need to link before we dont touch this will also force the reading of all the other files
set _dc_shell_status [link]
    if { $_dc_shell_status == 0} {
        echo {Info: Expecting Design Link but it did not?}
        exit 1
    } else {
        echo {Info: Link OK}
    }

# output a baseline design list
OutputHier $module.designlist.before_restructuring

# verify the design
check_design

# Normally the uniquify command would be run here but since we 
#  are preparing this design for the time budgeter we don't need to
#  at this time. That would involve grouping and ungrouping of the 
#  design to make it better match the physical and capacities of the
#  downstream tools.  Please see the gth_generic.dct file for examples
#  using the generic_hierarchy.tcl file as a side file to control
#  the building of this data.  Likewise you could use the ungroup and 
#  group commands in this file and do the same operations.



# At this point we would put in any execptions for the design:
#   modules which currently should be ignored by the budgeting process
# set_attribute ipxc_mb dont_budget true -type boolean

# BUT we choose not to do anything right now.

OutputHier $module.designlist

# also output a report that we can review for hierarchy.
set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $TDT_des] {_gtech_hier.}] {rpt}]
redirect $_file_out { report_hierarchy -full -nosplit }

# now write out the design so we have access to it for future stages:
# this is necessary to control where it puts the designs for future reference
foreach_in_collection d [get_designs] {
  current_design $d
  write -format db -output $TDT_gdbdir/$current_design.$TDT_gdbext
}

current_design $module
set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_gdbdir {/}] $TDT_des] {_hier.}] $TDT_gdbext] 
write -h -o $_file_out

exit
# end of file.

EOGTECH
}
##--------------------------------------------------------------
sub dump_gth_generic_script {
  my $fileref = shift;

print $fileref <<'EOGTECH_GEN';

# build_verilog_make.pl Generated Script - Edit with care
#  Sample GTECH script that automaticly produces the correct
#  hieararchy design list by using several Procedures.
# This script gives and example of the gth_global script
#  which can be design specific.  It uses the design_hierarchy.tcl
#  file to control what items are ungrouped and grouped to better
#  use the tool capacity.
#
# This is a set of procedures to produce hier 
source tcl/output_hier.tcl

# the the design to the top modules
set module $TDT_des

# source a file which contains bottom up compile lists for major blocks
# The file would look like:
# 
source $TDT_gtech_hier

# Modify the search path so that the already GTECHed designs are found:
set _search_path [format "%s%s" [format "%s%s" {./} $TDT_gdbdir ] {.0} ]
set search_path [concat  $_search_path $search_path]

# read the top of the database
read_file [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_gdbdir {.0/}] $TDT_des] {.}] $TDT_gdbext]

# set back to the top
current_design $module
# need to link before we dont touch this will also force the reading of all the other files
set _dc_shell_status [link]
    if { $_dc_shell_status == 0} {
        echo {Info: Expecting Design Link but it did not?}
        exit 1
    } else {
        echo {Info: Link OK}
    }

# output a baseline design list
OutputHier $module.designlist.before_restructuring

# verify the design
check_design

# Normally the uniquify command would be run here but since we 
#  are preparing this design for the time budgeter we don't need to
#  at this time.

# At this point we would put in any execptions for the design:
#   modules which currently should be ignored by the budgeting process
# set_attribute ipxc_mb dont_budget true -type boolean


# reset the design to the top
current_design $module
# If you have imbedded IP which have its own test structure you want
#  to eliminate it from being scored for test.
foreach  vdesign $TestSpecial {
   set _mycell [find cell -hier $vdesign]
   set_test_isolate $_mycell
   set_test_dont_fault $_mycell
   echo "Processing TestSpecial for: "
   query_objects $_mycell
}


# The IPXC hierarchy will be modified at this time because we want 20K
#  to 50K blocks to operate on.  These blocks are optimal for the design
#  budgeter and the size computers we have.

foreach  vdesign $UngroupLevel {
   current_design $vdesign
   ungroup -flatten -all
   echo "Processing Ungrouping for $current_design"
}

# reset the design to the top
current_design $module
foreach  vdesign $FlattenLevel {
   set _mycell [find cell -hier $vdesign]
   ungroup $_mycell
   echo "Processing Flattening for $_mycell"
}

# reset the design to the top
current_design $module
# set _mygroup [list]
# foreach  vdesign $GroupLevel {
#   set _mycell [find cell -hier $vdesign]
#   set _mygroup [concat $_mygroup $_mycell]
#   echo "Processing Grouping for $_mycell"
# }
# group $_mygroup -design_name $_mynewgroup -cell_name $_mynewgroup


current_design $module

# now block the clock and reset network from being touched by the 
#  synthesis tool. For example:
# dont_touch_network [find port {"clock100"}]
# dont_touch_network [find port {"reset"}]

# now relink the design because we have changed the hierarchy
set _dc_shell_status [link]
    if { $_dc_shell_status == 0} {
        echo {Info: Expecting Design Link but it did not?}
        exit 1
    } else {
        echo {Info: Link OK}
    }

OutputHier $module.designlist

# also output a report that we can review for hierarchy.
set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $TDT_des] {_gtech_hier.}] {rpt}]
redirect $_file_out { report_hierarchy -full -nosplit }

# now write out the design so we have access to it for future stages:
# this is necessary to control where it puts the designs for future reference
foreach_in_collection d [get_designs] {
  current_design $d
  write -format db -output $TDT_gdbdir/$current_design.$TDT_gdbext
}

current_design $module
set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_gdbdir {/}] $TDT_des] {_hier.}] $TDT_gdbext] 
write -h -o $_file_out

exit
# end of file.

EOGTECH_GEN
}


##--------------------------------------------------------------
## This section has all the GATE scripts included in it so that it is 
##  easy to isolate.
##--------------------------------------------------------------
sub dump_gates_makefile {
  my $subsref = shift;
  my $depthsref = shift;
  my $top_design = shift;
  my $makeinc = shift;
  my $depth = shift;
  my $fileref = shift;

  ## print STDERR "Debug: dumping makefile to level $depth\n";

  print $fileref <<"EOMAKEGATESHEAD";
##
## This file was auto-generated 
## by AFETC Generated Script - Edit with care
##
## All edits here may be overwritten
## Edit the include file to setup design and system parameters to keep
## I promise to honor them

## now the real design
EOMAKEGATESHEAD

  foreach( keys %$subsref ) {
    chomp;
    my $cdepth = $depthsref->{$_};
    my @subs = ();

    ##print $fileref "##" if $cdepth > $depth; 
    ## don't provide target for blocks below target depth

    ## Generate default rule for constraint file
    if( $_ eq $top_design) {
        ## FIXUP print $fileref "\${CONSPATH}/$_.2.\${TCONEXT} : \${CONSPATH}/$_.2.\${CONEXT}\n\n";
        ## print $fileref "\${CONSPATH}/$_.1.\${TCONEXT} : \${CONSPATH}/$_.1.\${CONEXT}\n\n";
        ## initial now setup properly from the start.
        print $fileref "\${CONSPATH}/$_.\${PASS}.\${TCONEXT} :";
        print $fileref " \${CONSPATH}/$_.\${TCONEXT}\n",
                "\t rm -f \$@; ln -s \$(<F) \$@;\n\n";
    } else {
        print $fileref "\${CONSPATH}/$_.2.\${TCONEXT} : \${CONSPATH}/$_.2.\${CONEXT}\n\n";
        print $fileref "\${CONSPATH}/$_.1.\${TCONEXT} : \${CONSPATH}/$_.1.\${CONEXT}\n\n";
        print $fileref "\${CONSPATH}/$_.0.\${TCONEXT} :";
        print $fileref "\n\t rm -f \$@; ln -s ../\${INITCONS} \$@;\n\n";
    }
    ##print $fileref "\ttouch \$@;\n\techo \"touching \$@\";\n\n";

    print $fileref "\${DBPATH}.\${PASS}/$_.\${DBEXT} : \${GDBPATH}/$_.\${GDBEXT}",
      "\\\n   \${CONSPATH}/$_.\${PASS}.\${TCONEXT}"; 

    if (defined ${$$subsref{$_}}[0]) {
      my $subdes;
      ##print STDERR "Debug: design $_ $cdepth vs $depth\n";
      my @offspring;
      if( $cdepth < $depth ) {
        @offspring = children_of $_, 0, $subsref;
      } else { 
        @offspring = children_of $_, 1, $subsref;
      }
      foreach $subdes (@offspring) {
        if( $cdepth >= $depth ) { ## down to lowest compile depth
          print $fileref "\\\n   \${GDBPATH}/$subdes.\${GDBEXT}";
          push @subs,  $subdes;
        } else { ## grab the DB from the search path but must have dependancy.
          print $fileref "\\\n   \${DBPATH}.\${PASS}/$subdes.\${DBEXT}";
          # push @subs,  $subdes;
        }
      }
    }
    print $fileref "\n";
    ##print $fileref "##" if $cdepth > $depth; 
    ## print STDERR "Debug: ", join("\t", @subs), "\n";
    ## don't provide target for blocks below target depth
    print $fileref "\t\${DCTSH} -x \"set TDT_des  $_;\\\n",
      "     set TDT_dont_use_cells \${XCELL};\\\n",
      "     set TDT_subs {", join(" ", @subs), "};\\\n",
      "     set TDT_pass \${PASS};set TDT_consdir \${CONSPATH};\\\n",
      "     set TDT_fpdir \${FLOORPLANPATH};\\\n",
      "     set TDT_custom_wireload \${WIRELOADS};\\\n",
      "     set TDT_foundry_lib \${FOUNDRY_LIB};\\\n",
      "     set TDT_initcons \${INITCONS};\\\n",
      "     set TDT_dbdir \${DBPATH};set TDT_dbext \${DBEXT};\\\n",
      "     set TDT_gdbdir \${GDBPATH};set TDT_gdbext \${GDBEXT};\\\n",
      "     set TDT_repdir \${REPSPATH};set TDT_conext \${TCONEXT};\"\\\n",
      "     -f \${DCTSCR} | tee \${LOGSPATH}/$_.dctsh.\${PASS}.\${LOGEXT}\n\n";
  }
print $fileref "\n## end of file\n";
}

##--------------------------------------------------------------
sub dump_dct_script {
  my $fileref = shift;

print $fileref <<'EODCTSCR';
# AFETC Generated Script - Edit with care
# generic compile script for
#  using and creating 
#  design budgeting passes 
#
# map efforts for compile runs
set TDT_pass0_map_effort {med}
set TDT_pass1_map_effort {med}
set TDT_pass2_map_effort {high}

if {  $TDT_gdbext == "" } {
   echo {Error: variable TDT_gdbext must be set to the GTECH DB file ext}
  exit 1
}
if {  $TDT_dbext == "" } {
   echo {Error: variable TDT_dbext must be set to the mapped DB file ext}
  exit 1
}

if {  $TDT_dbdir == "" } {
   echo {Error: variable TDT_db must be set to the directory containing mapped DBs}
  exit 1
}

set TDT_dbdir_src [format "%s%s" [format "%s%s"  $TDT_dbdir {.} ] [expr $TDT_pass - 1]]
set TDT_dbdir [format "%s%s" [format "%s%s"  $TDT_dbdir {.} ] $TDT_pass ]

if {  $TDT_gdbdir == "" } {
   echo {Error: variable TDT_gdb must be set to the directory containing GTECH DBs}
  exit 1
}
if {  $TDT_repdir == "" } {
   echo {Warning: TDT_repdir not set, will write reports to cwd}
  set TDT_repdir {.}
}
if { $TDT_initcons == "" } {
   echo {Error: initial constraint variable TDT_intcons not set}
  exit 1
}
if {  $TDT_consdir == "" } {
   echo {Error: constraint directory variable TDT_consdir not set}
  exit 1
}
if {  $TDT_subs == "" } {
   set TDT_subs [list]
}
if {  $TDT_des == "" } {
   echo {Error: design not specified in TDT_des variable}
  exit 1
}

if { $TDT_pass >= 1 } { 
  # Modify the search path so that if this is the bottom it will find its source.
  set _search_path [format "%s%s"  {./} $TDT_dbdir_src ]
  set search_path [concat  $_search_path $search_path]
  # Modify the search path so that the already optimized childen are found first:
  set _search_path [format "%s%s"  {./} $TDT_dbdir ]
  set search_path [concat  $_search_path $search_path]
} 
echo [format "%s%s" {Search Path is: } $search_path]
# else No search path for pass 0 as we want each db file to stand on
# its own.  This was a real pain to figure out.

if {  $TDT_pass < 2 } {
   echo {Info: reading all GTECH subdesigns}
   foreach TDT_gdbsub $TDT_subs {
   read_file [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_gdbdir {/}] $TDT_gdbsub] {.}] $TDT_gdbext]
   set_dont_touch $TDT_gdbsub {false}
  }
  # relys on search path to find the already mapped DB files.
  read_file [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_gdbdir {/}] $TDT_des] {.}] $TDT_gdbext]
} else {
   # relys on search path to find subsequent designs
   echo {Info: reading mapped design}
   foreach TDT_dbsub $TDT_subs {
     read_file [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_dbdir_src {/}] $TDT_dbsub] {.}] $TDT_dbext]
     set_dont_touch $TDT_dbsub {false}
   }
   read_file [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_dbdir_src {/}] $TDT_des] {.}] $TDT_dbext]
}

set _dc_shell_status [link]
    if { $_dc_shell_status == 0} {
        echo {Info: Expecting Design Not to LINK}
    } else {
        echo {Info: Link OK but NOT Expected?}
    }

#### ********************************************************************************
## grab the Environment Conditions setup in the .dc_setup file.
#### ********************************************************************************
set_operating_conditions -max $operating_conditions_max -min $operating_conditions_min
set_wire_load_selection_group -library $foundry_library_basename $wire_load_selection_group
set_wire_load_mode $wire_load_mode
set auto_wire_load_selection {true}
set_timing_range -library $foundry_library_basename {SLOW_RANGE FAST_RANGE}
#### ********************************************************************************

# custom wireload files if the side file exists
#  The wireloads only exist in memory
#
set _my_applied_wireload {}
if {  $TDT_pass >= 1 } {

   if { [file exists $TDT_custom_wireload] } {
       echo [format "%s%s" {Info: Reading Wireload Tcl File - } $TDT_custom_wireload]
       source $TDT_custom_wireload
       # see if we have a local library already
       set _lib_file [format "%s%s%s%s%s" $TDT_dbdir {/my_} $TDT_foundry_lib {.} $TDT_dbext] 
       # now interate on the file until we have read in all the wireloads and attached
       # them to the target library
       foreach _my_fp $WireLoadFiles {
          set _wireload_file [format "%s%s" [format "%s%s" $TDT_fpdir {/}] $_my_fp]
          if { [file exists $_wireload_file] } {
             update_lib $TDT_foundry_lib $_wireload_file
             echo [format "%s%s" {Info: Reading in Wireload File } $_wireload_file]
          } else {
             echo [format "%s%s" [format "%s%s" {Warning: Wireload File } $_wireload_file] { Not Found.}]
          }
       }
    
       # now that we have the wireload models we need to attach the correct wireload model to 
       # our design so that we can perform further optimizations
    
       # first find a matching wireload table that is suppose to be used for the current_module
       foreach _wl $WireLoads {
          if { [lsearch $designWireLoad($_wl) $current_design] >= 0 } {
             echo [format "%s%s" {Info: Found Wireload } $designWireLoad($_wl)] 
             if { [set_wire_load $_wl -mode enclosed] } {
                 # remove the auto select if we have our own as it defaults to true
                 set auto_wire_load_selection false
                 # store the wireload for later application
                 set _my_applied_wireload $_wl
                 echo [format "%s%s" {Info: Applied DesignWireLoad } $_wl] 
             }
             break
             # now force dc to know the new wireload
             update_timing
          } else {
             echo [format "%s%s" {Info: No DesignWireLoad Found for } $current_design] 
          }
       }
  } else {
    echo [format "%s%s" {Info: No Custom Wireload File: } $TDT_custom_wireload ]
  }
}


# since most of the designs are not area constrainted we removed the rpls to
# ensure the fastest design.
echo {Warning: setting dont_use on all rpl implementations in standard.sldb}
set_dont_use standard.sldb/*/rpl
# the removal of all rpls was a little extreme as this cause a very interesting
#  side effect of removing several logic operators.  This puts back the compares
#  which seems to fix the problem.
remove_attribute standard.sldb/*cmp*/rpl dont_use

if {  $TDT_pass == 0 } {
   echo {Info: including initial constraints}
   source $TDT_initcons

} else {
   echo [format "%s%s"  {Info: including design constraints for } $current_design]
   set _constraint_file_in [format "%s%s"  [format "%s%s"  [format "%s%s" [format "%s%s" [format "%s%s" [format "%s%s" $TDT_consdir {/}] $current_design] {.}] $TDT_pass] {.}] $TDT_conext]
   source -verbose $_constraint_file_in
}

# now reapply the wireload because the constraint file will often
#  replace it with its own if the budgeter did not see the wireloads.
#  This will often happen on the pass=0 budget because it was a quick budget
if {$_my_applied_wireload != ""} {
  # grab the operating conditions setup in the .dc_setup file.
  set_operating_conditions -max $operating_conditions_max -min $operating_conditions_min
  set_wire_load $_my_applied_wireload -mode $wire_load_mode
} else {
   #### ********************************************************************************
   ## grab the Environment Conditions setup in the .dc_setup file - if not using custom WL
   #### ********************************************************************************
   set_operating_conditions -max $operating_conditions_max -min $operating_conditions_min
   set_wire_load_selection_group -library $foundry_library_basename $wire_load_selection_group
   set_wire_load_mode $wire_load_mode
   set auto_wire_load_selection {true}
   set_timing_range -library $foundry_library_basename {SLOW_RANGE FAST_RANGE}
   #### ********************************************************************************
}

# set _report_file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $current_design] {.chk.rpt}]
# redirect $_report_file_out { check_timing }
echo {Uniquifying design to solve non-unique instantiations}
uniquify
# redirect -append $_report_file_out { check_design }

# grab the excluded cells script if necessary
if { $TDT_dont_use_cells == ""} {
    echo {Info: No Excluded Cells}
} else {
    echo [format "%s%s"  {Info: Reading Excluded Cells List: } $TDT_dont_use_cells]
    source $TDT_dont_use_cells
}

# The fix_multiple_port_nets is used here on each lowest level of the design. This
#  switch is important to allow us to complete ECO cycles with the Avant! Apollo
#  tool.  In many designs we will attach an internal net to many outputs.
#  This had an intesting side-effect when we ECO'ed the design.  This switch will
#  force DC to put in a buffere to all the outputs.  With the buffer in place we 
#  should then be able to force DC to keep the names consistent.
set_fix_multiple_port_nets -feedthroughs -outputs

# each design is allowed a custom compile script that has the same format as below
#  but allows the user to control how this module gets compiled.  This is setup to allow
#  the user flexiblity in the design.
set _compile_script [format "%s%s" $TDT_des {.scr}]
if { [file exists $_compile_script] } {
    echo [format "%s%s" {Info: Reading Compile Script - } $_compile_script]
    source -verbose $_compile_script
} else {
  echo [format "%s%s"  {Info: compiling design } $current_design]
  if {  $TDT_pass == 0 } {
     compile -scan -map $TDT_pass0_map_effort
  } else {
     if {  $TDT_pass == 1 } {
       compile -scan -map $TDT_pass1_map_effort
     } else {
       ##
       # report the current DW implementations for later review.
       ## HARDCODED path:
       source tcl/check_dw.tcl
       check_dw
       # if we are on the last passes then ungroup the design ware components
       # as synopsys should have made good choices by now and we could get a little
       # more optimization by removing this layer of hierarchy. 
       ## Hard pathed TCL script.
#       source tcl/ungroup_dw.tcl
#       ungroup_dw -hier
       compile -scan -incr -map $TDT_pass2_map_effort
     }
  }
}

set_dont_touch $current_design {true}
if {  $TDT_subs != [list] } {
   set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_dbdir {/}] $current_design] {.}] $TDT_dbext] 
   echo [format "%s%s" {Info: Writing Hierarchy Database to: } $_file_out]
   write -h -o $_file_out
} else {
   set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_dbdir {/}] $current_design] {.}] $TDT_dbext] 
   echo [format "%s%s" {Info: Writing Flat Database to: } $_file_out]
   write -o $_file_out
}

# now report the design so we know lots of knowledge:
report_design

# this alters comparison with hier compile 
set _report_file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $current_design] {.pass}] $TDT_pass] {.qor.rpt}]
# redirect $_report_file_out { report_qor }
set _report_file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $current_design] {.pass}] $TDT_pass] {.tim.rpt}] 
# redirect $_report_file_out { report_timing -max_path 10 -nworst 10 -path short }

#
exit
# end of file

EODCTSCR

}

##--------------------------------------------------------------
sub dump_dct_hier_script {
  my $fileref = shift;

print $fileref <<'EODCTHSCR';
# AFETC Generated Script - Edit with care
# Generations of a Hiearchy with Timing Constraints Design Database for
#  use with downstream tools.
#
#
# change the directory path so that the data for this pass is found.
set TDT_dbdir [format "%s%s" [format "%s%s"  $TDT_dbdir {.} ] $TDT_pass ]

# Modify the search path so everyone is found.
set _search_path [format "%s%s"  {./} $TDT_dbdir ]
set search_path [concat  $_search_path $search_path]

# read and link design using search path to build it.
read_file [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_dbdir {/}] $TDT_des] {.}] $TDT_dbext]
set _dc_shell_status [link]
    if { $_dc_shell_status == 0} {
        echo {Info: Expecting Design to LINK but did not?}
        exit 1
    } else {
        echo {Info: Link OK}
    }

#### ********************************************************************************
## grab the Environment Conditions setup in the .dc_setup file.
#### ********************************************************************************
set_operating_conditions -max $operating_conditions_max -min $operating_conditions_min
set_wire_load_selection_group -library $foundry_library_basename $wire_load_selection_group
set_wire_load_mode $wire_load_mode
set auto_wire_load_selection {true}
set_timing_range -library $foundry_library_basename {SLOW_RANGE FAST_RANGE}
#### ********************************************************************************

# custom wireload files if the side file exists
#  The wireloads only exist in memory
#
if {  $TDT_pass >= 1 } {

   if { [file exists $TDT_custom_wireload] } {
       echo [format "%s%s" {Info: Reading Wireload Tcl File - } $TDT_custom_wireload]
       source $TDT_custom_wireload
       # see if we have a local library already
       set _lib_file [format "%s%s%s%s%s" $TDT_dbdir {/my_} $TDT_foundry_lib {.} $TDT_dbext] 
       # now interate on the file until we have read in all the wireloads and attached
       # them to the target library
       foreach _my_fp $WireLoadFiles {
          set _wireload_file [format "%s%s" [format "%s%s" $TDT_fpdir {/}] $_my_fp]
          if { [file exists $_wireload_file] } {
             update_lib $TDT_foundry_lib $_wireload_file
             echo [format "%s%s" {Info: Reading in Wireload File } $_wireload_file]
          } else {
             echo [format "%s%s" [format "%s%s" {Warning: Wireload File } $_wireload_file] { Not Found.}]
          }
       }
    
       # now that we have the wireload models we need to attach the correct wireload model to 
       # our design so that we can perform further optimizations
    
       # first find a matching wireload table that is suppose to be used for the current_module
       foreach _wl $WireLoads {
          if { [lsearch $designWireLoad($_wl) $current_design] >= 0 } {
             echo [format "%s%s" {Info: Found Wireload } $designWireLoad($_wl)] 
             if { [set_wire_load $_wl -mode enclosed] } {
                 # remove the auto select if we have our own as it defaults to true
                 set auto_wire_load_selection false
                 echo [format "%s%s" {Info: Applied DesignWireLoad } $_wl] 
             }
             break
             # now force dc to know the new wireload
             update_timing
          } else {
             echo [format "%s%s" {Info: No DesignWireLoad Found for } $current_design] 
          }
       }
  } else {
    echo [format "%s%s" {Info: No Custom Wireload File: } $TDT_custom_wireload ]
  }
}


# grab the excluded cells script if necessary
if { $TDT_dont_use_cells == ""} {
    echo {Info: No Excluded Cells}
} else {
    echo [format "%s%s"  {Info: Reading Excluded Cells List: } $TDT_dont_use_cells]
    source $TDT_dont_use_cells
}

# read in the top level constraints so they are applied.
set _constraint_file_in [format "%s%s" [format "%s%s" $TDT_des {.}] $TDT_conext]
source -verbose $_constraint_file_in


# generate a qor report
set _report_file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $TDT_des] {.pass}] $TDT_pass] {.qor.rpt}] 
redirect $_report_file_out { report_qor } 

# modify the attributes before we start working with the design.
foreach_in_collection TDT_cd [get_designs] { 
  current_design $TDT_cd 
  if {[get_attribute $current_design dont_budget] == "true" } { 
     set_dont_touch {true} 
     } else { 
       remove_attribute $current_design dont_touch
     }
  } 

# reset the design to the top

current_design $TDT_des
set _dc_shell_status [link]
    if { $_dc_shell_status == 0} {
        echo {Info: Expecting Design to LINK but did not?}
        exit 1
    } else {
        echo {Info: Link OK}
    }
# check_design report
set _report_file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $current_design] {_hier.chk.rpt}]
redirect $_report_file_out { check_design }

# Loop Check Report
set _report_file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $current_design] {_hier.loop.rpt}]
redirect $_report_file_out { report_timing -loops }

# Latch Checking
set _report_file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $current_design] {_hier.latch.rpt}]
redirect $_report_file_out { all_registers -level_sensitive }

# Note HardCoded Name
set _compile_script [format "%s%s" $TDT_des {_hier.scr}]
if { [file exists $_compile_script] } {
    echo [format "%s%s" {Info: Reading Compile Script - } $_compile_script]
    source -verbose $_compile_script
} else {
    # note hard coded name.
    set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s" [format "%s%s"  $TDT_dbdir {/}] $current_design] {_hier}] {.}] $TDT_dbext] 
    echo [format "%s%s" {Info: Writing Hierarchy Database to: } $_file_out]
    write -h -o $_file_out
}

# foreach_in_collection TDT_cd [get_designs] { 
#  current_design $TDT_cd 
#  set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_dbdir {/}] $current_design] {.}] $TDT_dbext]
#  write -format db -output $_file_out
# } 

exit
# end of file

EODCTHSCR

}
      
##--------------------------------------------------------------
sub dump_dcc_script {
  my $fileref = shift;

print $fileref <<'EODCCSCR';
# AFETC Generated Script - Edit with care
# Generation of the chip level combined db file for use with down
#  stream tools.  This file must have a much of the constraint
#  information as possible to use with the downstream tools.
#
#
# change the directory path so that the data for this pass is found.
set TDT_dbdir [format "%s%s" [format "%s%s"  $TDT_dbdir {.} ] $TDT_pass ]


# The top level design has already been read in at this point we now need to
#  process the top level files.


# Modify the search path so the source is found for the tap controller
set _old_search_path $search_path
set _search_path [format "%s%s"  {./} $TDT_rtl ]
set search_path [concat  $_search_path $search_path]

set _file_in [format "%s%s" $TDT_des {_tap_state.v}]
read_verilog $_file_in
set _file_in [format "%s%s" $TDT_des {_tap.v}]
read_verilog $_file_in

current_design ${TDT_des}_tap
ungroup -all -flatten
compile -map_effort med
dont_touch $current_design
set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_dbdir {/}] $current_design] {.}] $TDT_dbext] 
write -o $_file_out


# now get the chip level design with pads.
set _file_in [format "%s%s" $TDT_des {.v}]
read_verilog $_file_in

current_design $TDT_des;

# since we read in the hierarchy file life should be find and no search path 
#  changes are necessary.
set search_path $_old_search_path]

# reset the search path so all the db files are found if necessary
# set _search_path [format "%s%s"  {./} $TDT_dbdir ]
# set search_path [concat  $_search_path $_old_search_path]

set _dc_shell_status [link]
    if { $_dc_shell_status == 0} {
        echo {Info: Expecting Design Link but it did not?}
        exit 1
    } else {
        echo {Info: Link OK}
    }

# read in the top level constraints so they are applied.
# set _constraint_file_in [format "%s%s" [format "%s%s" $TDT_des {.}] $TDT_conext]
# source $_constraint_file_in

# generate a qor report
# set _report_file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $TDT_des] {.pass}] $TDT_pass] {.qor.rpt}] 
# redirect $_report_file_out { report_qor } 

# reset the design to the top
current_design $TDT_des

# check_design report
set _report_file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $current_design] {_hier.chk.rpt}]
redirect $_report_file_out { check_design }

# Loop Check Report
set _report_file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $current_design] {_hier.loop.rpt}]
redirect $_report_file_out { report_timing -loops }

# Latch Checking
set _report_file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $current_design] {_hier.latch.rpt}]
redirect $_report_file_out { all_registers -level_sensitive }

# note hard coded name.
set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_dbdir {/}] $current_design] {.}] $TDT_dbext] 
write -h -o $_file_out

exit
# end of file

EODCCSCR

}

##--------------------------------------------------------------
sub dump_tc_script {
  my $fileref = shift;

print $fileref <<'EOTCSCR';
# AFETC Generated Script - Edit with care
# Test Compiler Simple Script
#  
#  Read in hierarchy DB with everything setup
#   walk through each level of hierarcy to ensure that rules are met.
#   insert scan
#   test only the top level.
#   insert jtag
#   dont touch the jtag
#   test again.
#   complete.
#  
#
# Modify the search path so everyone is found.
# Search path is unnecessary
# set _search_path [format "%s%s"  {./} $TDT_dbdir ]
# set search_path [concat  $_search_path $search_path]


# modify the db location so that everyone is looking in the right location.
set TDT_dbdir_src [format "%s%s" [format "%s%s"  $TDT_dbdir {.} ] [expr $TDT_pass - 1]]
set TDT_dbdir [format "%s%s" [format "%s%s"  $TDT_dbdir {.} ] $TDT_pass ]

# build the new directory if necessary
exec mkdir $TDT_dbdir

# read and link design using search path to build it.
set _file_in [format "%s%s" [format "%s%s" [format "%s%s" [format "%s%s"  $TDT_dbdir_src {/} ] $TDT_des] {.}] $TDT_dbext]
read_db $_file_in
# linking is unnecessary because we have all the data
set _dc_shell_status [link]
    if { $_dc_shell_status == 0} {
        echo {Info: Expecting Design Link but it did not?}
        exit 1
    } else {
        echo {Info: Link OK}
    }

# now lets reset the design so we have no preconcieved ideas of what constraints are applied.
reset_design

# reset the design to the top and dump the DB so we have a match.
current_design $TDT_des

# setup the JTAG stuff
set_attribute current_design jtag_inserted true -type boolean
set_signal_type jtag_trst "ntrst"
set_signal_type jtag_tck "tck"
set_signal_type jtag_tms "tms"
set_signal_type jtag_tdo "tdo"
set_signal_type jtag_tdi "tdi"

# the user now needs to have a scan list of pins for input and output and any other special commands here.
set _compile_script [format "%s%s" $TDT_des {.scan}]
if { [file exists $_compile_script] } {
    echo [format "%s%s" {Info: Reading Scan Script - } $_compile_script]
    source -verbose $_compile_script
}

# setup the scan configuration
set_scan_configuration  \
      -methodology full_scan \
      -style multiplexed_flip_flop \
      -chain_count 31 \
      -replace false \
      -bidi_mode input \
      -rebalance true

set _excluded_registers [all_registers -clock jtag50]    
set_scan_element false $_excluded_registers

set _report_file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $current_design] {.}] $TDT_pass] {.before.check_scan}] 
redirect $_report_file_out { check_scan } 

set _report_file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $current_design] {.}] $TDT_pass] {.before.preview_scan}] 
redirect $_report_file_out { preview_scan -show all } 


set test_dont_fix_constraint_violations true
# now put in the scan 
insert_scan -ignore_compile_design_rules


set _report_file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $current_design] {.}] $TDT_pass] {.after.check_scan}] 
redirect $_report_file_out { check_scan } 

set _report_file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $current_design] {.}] $TDT_pass] {.after.report_test}] 
redirect $_report_file_out { report_test -scan_path } 


# a lot of extra stuff I am not sure that I want to delete:
# get a bottom up list that was created for this design; the variable set is TDT_ordered_designs
source [format "%s%s" $TDT_des {.ordered.tcl}]

# setup some clock stuff we will use later
set _half_period [expr $test_default_period / 2]
set _waveform [list $test_default_delay $_half_period]

# setup the scan configuration
set_scan_configuration  \
      -dedicated_scan_ports false \
      -methodology full_scan \
      -style multiplexed_flip_flop \
      -rebalance true


# look through all the designs and check there test functions.
foreach  vdesign $TDT_ordered_designs {
    current_design $vdesign
    # get all the registers and gather the clock pins then find out which net is really is
    # all of this would be easier if everyone used a common name for the clocks.  The design
    # team should really work on consistant nameing of reset and clock.
    set _register_c [all_registers -no_hier -clock_pin]    
    set _clock_pins [all_fanin -to $_register_c -start]
    create_test_clock $_clock_pins -waveform $_waveform

    set _report_file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $current_design] {.pass}] $TDT_pass] {.before.testcheck}] 
    redirect $_report_file_out { check_test } 
}

current_design $TDT_des

# LOTS COMMENTED OUT BELOW BECAUSE IT DOESN'T WORK
# now insert the scan chain
insert_scan

foreach  vdesign $TDT_ordered_designs {
    current_design $vdesign
    set _register_c [all_registers -no_hier -clock_pin]    
    set _clock_pins [all_fanin -to $_register_c -start]
    create_test_clock $_clock_pins -waveform $_waveform
    # check violations
    set _report_file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $current_design] {.pass}] $TDT_pass] {.after.testcheck}] 
    redirect $_report_file_out { check_test } 
    # check module level patterns after scan insertions
    set _report_file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $current_design] {.pass}] $TDT_pass] {.after.testpattern}] 
    redirect $_report_file_out { create_test_patterns -sample 3 } 
}

# current_design $TDT_des
# now generate tests for 5% of the design to validate the ATPG function.
# create_test_patterns -sample 5

# now insert JTAG
#  Lots of commands

current_design $TDT_des
#check_test
# write out the scan and jtaged design
# set this varaible to make sure we have the real data.
set atpg_keep_faults_data true

# now write the data out.
set _file_out [format "%s%s" [format "%s%s"  [format "%s%s" [format "%s%s" $TDT_dbdir {/}] $TDT_des] {.}] $TDT_dbext]
write -h -o $_file_out


# read in the chip logic and link
#  Run ATPG
#create_test_patterns
#write_test -format???

exit
# end of file

EOTCSCR

}

##--------------------------------------------------------------
sub dump_dct_area_script {
  my $fileref = shift;

print $fileref <<'EOAREASCR';
# AFETC Generated Script - Edit with care
#  Script for dumping area calculation of the design hierarchy 
#
# modify the dbdir for this passes work.
set TDT_dbdir [format "%s%s" [format "%s%s"  $TDT_dbdir {.} ] $TDT_pass ]
# Modify the search path so everyone is found.
set _search_path [format "%s%s"  {./} $TDT_dbdir ]
set search_path [concat  $_search_path $search_path]

# always generate an error
set _basescript {NEED_TO_WRITE}
if ![string compare $_basescript NEED_TO_WRITE] {
   echo {Error: Need to Build Design Specific Area Script}
  exit 1
}

# the the design to the top modules
set module $TDT_des

# read and link design using search path to build it, note the hierarchy file name
read_file [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s" [format "%s%s" $TDT_dbdir {/}] $TDT_des] {_hier}] {.}] $TDT_dbext]
# no linking necessary if using hierarchy design
# link;

# get a bottom up list that was created for this design; the variable set is TDT_ordered_designs
source [format "%s%s" $TDT_des {.ordered.tcl}]

# modify the attributes before we start working with the design.
foreach TDT_cd $TDT_ordered_designs { 
  current_design $TDT_cd 
  set _report_file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $current_design] {.area.rpt}]
  redirect $_report_file_out { report_reference }
  } 

# reset the design to the top

exit
# end of file

EOAREASCR

}

##--------------------------------------------------------------
sub dump_dct_layout_script {
  my $fileref = shift;

print $fileref <<'EOLAYOUTSCR';
# AFETC Generated Script - Edit with care
#  Script for dumping data required by layout tools
#

# always generate an error
set _basescript {NEED_TO_WRITE}
if ![string compare $_basescript NEED_TO_WRITE] {
   echo {Error: Need to Build Design Specific Area Script}
  exit 1
}

# the the design to the top modules
set module $TDT_des

# read and link design using search path to build it, ASSUME it was read in on the command line
# link;

## Foundary specific modifications for VLSI
set _fileout [format "%s%s"  [format "%s%s"  [format "%s%s" [format "%s%s" \${LAYOUTPATH} {/}] \${CHIP_DESIGN}] {.\${PASS}}] {.changed.names}]
redirect  $_fileout { report_names -rules VLSI_CELL -hierarchy -nosplit }
redirect -append $_fileout { report_names -rules VLSI_PORT -hierarchy -nosplit }
redirect -append $_fileout { report_names -rules VLSI_NET -hierarchy -nosplit }
change_names -rules VLSI_CELL -hierarchy -verbose
change_names -rules VLSI_PORT -hierarchy -verbose
change_names -rules VLSI_NET -hierarchy -verbose

# grab a tcl script to report the timing of each level.
# NOTE HARDCODED
source tcl/dump_timing.tcl

# grab file with stuff setup in it.
source $TDT_hierarchy

# modify the attributes before we start working with the design.
foreach TDT_cd $LayoutBlocksHierarchy { 
  current_design $TDT_cd 
  set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_layoutdir {/}] $current_design] {.v}]
  write -hierarchy -format verilog -output $_file_out
  DumpTiming $current_design $TDT_pass $TDT_layoutdir
  } 

foreach TDT_cd $LayoutBlocksFlat { 
  current_design $TDT_cd 
  set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_layoutdir {/}] $current_design] {.v}]
  write -format verilog -output $_file_out
  DumpTiming $current_design $TDT_pass $TDT_layoutdir
  } 

# reset the design to the top and dump the DB so we have a match.
current_design $TDT_des

set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_layoutdir {/}] $current_design] {.db}]
write -hierarchy -format db -output $_file_out

exit
# end of file

EOLAYOUTSCR

}

##--------------------------------------------------------------
sub dump_dct_floorplan_script {
  my $fileref = shift;

print $fileref <<'EOFLOORPLANSCR';
# AFETC Generated Script - Edit with care
#  Script for dumping data required by layout tools
#

# always generate an error
set _basescript {NEED_TO_WRITE}
if ![string compare $_basescript NEED_TO_WRITE] {
   echo {Error: Need to Build Design Specific FP Script}
  exit 1
}

# the the design to the top modules
set module $TDT_des

# read and link design using search path to build it, ASSUME it was read in on the command line
# link;

# grab a tcl script to report the timing of each level.
# NOTE HARDCODED
source tcl/dump_timing.tcl

# grab file with stuff setup in it.
source $TDT_hierarchy

# modify the attributes before we start working with the design.
foreach TDT_cd $LayoutBlocksHierarchy { 
  current_design $TDT_cd 
  DumpTiming $current_design $TDT_pass $TDT_fpdir
  } 

foreach TDT_cd $LayoutBlocksFlat { 
  current_design $TDT_cd 
  DumpTiming $current_design $TDT_pass $TDT_fpdir
  } 

# reset the design to the top and dump the DB so we have a match.
current_design $TDT_des

set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_fpdir {/}] $current_design] {.v}]
write -hierarchy -format verilog -output $_file_out

exit
# end of file

EOFLOORPLANSCR

}

##--------------------------------------------------------------
sub dump_dct_test_script {
  my $fileref = shift;

print $fileref <<'EOTESTPLANSCR';
# AFETC Generated Script - Edit with care
#  Script for preparing a design for TetraMax
#

# always generate an error
set _basescript {NEED_TO_WRITE}
if ![string compare $_basescript NEED_TO_WRITE] {
   echo {Error: Need to Build Design Specific TetraMax Script}
  exit 1
}

#
# This script takes in a DB file and outputs the verilog and tetramax
#  complient protocal file.
#
# change the directory path so that the data for this pass is found.
set TDT_dbdir [format "%s%s" [format "%s%s"  $TDT_dbdir {.} ] $TDT_pass ]

# build the top instance because we always are going back to it.
set TDT_des_instance [format "%s%s" {/} $TDT_des]

# set back to the top
current_design $TDT_des
set _dc_shell_status [link]
    if { $_dc_shell_status == 0} {
        echo {Info: Expecting Design Link but it did not?}
        exit 1
    } else {
        echo {Info: Link OK}
    }

# defaults that must be setup:
set_test_hold 1 {"scantestmode" "n_disable_all"}
set_signal_type test_scan_enable  test_scan_enable

# now all the JTAG signals:
set_signal_type jtag_tdi tdi
set_signal_type jtag_tdo tdo
set_signal_type jtag_tms tms
set_signal_type jtag_tck tck
set_signal_type jtag_trst ntrst

# now for the configuration data:
set_scan_configuration -existing_scan true
set_attribute $current_design jtag_inserted true -type boolean

# the Stil format must know what type it is matching to.
test_stil_netlist_format = verilog

# now lets add the reports for scan:
set _file_in [format "%s%s" $TDT_des {.scanports}]
if { [file exists $_file_in] } {
   echo [format "%s%s" {Info: Reading ScanPort Configuration File - } $_file_in]
   source -verbose $_file_in
   
} else {
   echo {Info: No ScanPort Configuration File}
   exit
}

set _report_file_out [format "%s%s%s%s%s%s"  $TDT_repdir {/} $TDT_des {.} $TDT_pass {.check_scan_pre.rpt}] 
redirect $_report_file_out { check_test } 

# write out the test protocol so we can edit it:
set _tpf_file_out [format "%s%s%s%s"  $TDT_dbdir {/} $TDT_des {.tpf}] 
set _tpf_file_in [format "%s%s%s%s"  $TDT_dbdir {/} $TDT_des {.edit.tpf}] 
write_test_protocol -out $_tpf_file_out

# now call some perl program that edits the protocol with the special sequences:
#FIXUP:
#exec bin/ipxc_edit_tpf.pl -i $_tpf_file_out -o $_tpf_file_in
#read_init_protocol $_tpf_file_in

#set _report_file_out [format "%s%s%s%s%s%s"  $TDT_repdir {/} $TDT_des {.} $TDT_pass {.check_scan_post.rpt}] 
#redirect $_report_file_out { check_test } 

# now write out the STIL protocol for TetraMax
set _spf_file_out [format "%s%s%s%s"  $TDT_dbdir {/} $TDT_des {.spf}] 
write_test_protocol -format stil -out $_spf_file_out

# write the db out now so we can use it.
# note hard coded name.
set _file_out [format "%s%s%s%s"  $TDT_dbdir {/} $TDT_des {.v}] 
write -format verilog -h -o $_file_out

exit
# end of file

EOTESTPLANSCR

}

##--------------------------------------------------------------
sub dump_init_cons {
  my $fileref = shift;
  print $fileref <<'EOCONS';

# AFETC Generated Script - Edit with care
# initial constraints for building design
#   for budgeting 
set _period {NEED_TO_SET_PERIOD}
if ![string compare $_period NEED_TO_SET_PERIOD] {
   echo {Error: Need to specify tightest period in initial cons file}
  exit 1
}
set _half_period [expr $_period / 2]
set _waveform [list 0 $_half_period]
set _multiplier 2
set _input_delay [expr 0.65 * $_period]
set _output_delay [expr 0.35 * $_period]

set _inputs [all_inputs]
set _outputs [all_outputs]
set _register_c [all_registers -no_hier -clock_pin]

if {  $_register_c == [list] } {
   set _clock_pins [list]
} else {
   set _clock_pins [all_fanin -to $_register_c -start]
  create_clock $_clock_pins -name {reg2reg} -period $_period -waveform $_waveform
  set_multicycle_path $_multiplier -from {reg2reg} -to {reg2reg}
}

create_clock -name {simple} -period $_period -waveform $_waveform
set_input_delay $_input_delay -clock {simple} [remove_from_collection $_inputs $_clock_pins]
if { $_outputs != {} } {
   set_output_delay $_output_delay -clock {simple} $_outputs
}
# end of file.

EOCONS
}

##--------------------------------------------------------------
sub dump_generic_compile_scr {
  my $fileref = shift;
  print $fileref <<'EOGSCR';

# AFETC Generated Script - Edit with care
#  Generic example of a compile script each module may
#  have a compile script based on this one.
echo [format "%s%s"  {Info: Custom Compiling Design } $current_design]
if {  $TDT_pass == 0 } {
   compile -scan -map $TDT_pass0_map_effort
} else {
  if {  $TDT_pass == 1 } {
     compile -scan -map $TDT_pass1_map_effort
  } else {
     # if in pass 2 or greater we want to ungroup the designware components.
#     tcl/source ungroup_dw.tcl
#     ungroup_dw -hier
     compile -scan -incr -map $TDT_pass2_map_effort
  }
}
#
# end of file.

EOGSCR
}

##--------------------------------------------------------------
sub dump_generic_hier_compile_scr {
  my $fileref = shift;
  print $fileref <<'EOGHSCR';

# AFETC Generated Script - Edit with care
#  Generic example of a compile script each module may
#  have a compile script based on this one.
echo [format "%s%s"  {Info: Custom Compiling Design } $current_design]
if {  $TDT_pass == 0 } {
   compile -scan -map $TDT_pass0_map_effort
} else {
  if {  $TDT_pass == 1 } {
     compile -scan -map $TDT_pass1_map_effort
  } else {
     # if in pass 2 or greater we want to ungroup the designware components.
     set designware_cells [filter [find cell] {@is_synlib_operator==true}]
     set_ungroup $designware_cells true
     compile -scan -incr -map $TDT_pass2_map_effort
  }
}

# note hard coded name.
set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s" [format "%s%s"  $TDT_dbdir {/}] $current_design] {_hier}] {.}] $TDT_dbext] 
write -h -o $_file_out

# if you have optimized across boundarys you need to write out the designs.
foreach_in_collection TDT_cd [get_designs] { 
    current_design $TDT_cd 
    set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_dbdir {/}] $current_design] {.}] $TDT_dbext]
    write -format db -output $_file_out
} 


#
# end of file.

EOGHSCR
}

##--------------------------------------------------------------
sub dump_generic_wireload_scr {
  my $fileref = shift;
  print $fileref <<'EOWLSCR';

# AFETC Generated Script - Edit with care
#  Generic example of a wireload script for design.
# 
# Assume Avante Planet Tools.
# 

# list of wireload files found in the Floorplanning directory
set WireLoadFiles { \
       my_top.wl \
       my_sub.wl \
    }

# List of wireloads in the wireload files.
set WireLoads { \
        GROUP_top_wl \
        my_top_wl \
        GROUP_sub_wl \
        my_sub_wl \
    }

# Associated list of wireloads and the designs they are used on
#   Should be at least one entry per WireLoads from above.
# Every wireload from above must be accounted for here even if 
#  there is no design associated with them.
set designWireLoad(GROUP_top_wl) { \
        my_top \               
    }

set designWireLoad(my_top_wl) {}
set designWireLoad(GROUP_sub_wl) {}
set designWireLoad(my_sub_wl) {}
#
# end of file.

EOWLSCR
}

##--------------------------------------------------------------
sub dump_generic_wl_dct {
  my $fileref = shift;
  print $fileref <<'EOWLDCT';

# AFETC Generated Script - Edit with care
# Purpose: To build a stand alone library with our wireloads in it.
#
#

# set the output DB location
set TDT_dbdir [format "%s%s" [format "%s%s"  $TDT_dbdir {.} ] $TDT_pass ]

# check if the wireload file exists
if { [file exists $TDT_custom_wireload] } {
    echo [format "%s%s" {Info: Reading Wireload Tcl File - } $TDT_custom_wireload]
    source $TDT_custom_wireload
    # now interate on the file until we have read in all the wireloads and attached
    # them to the target library
    foreach _my_fp $WireLoadFiles {
      set _wireload_file [format "%s%s" [format "%s%s" $TDT_fpdir {/}] $_my_fp]
      if { [file exists $_wireload_file] } {
        update_lib $TDT_foundry_lib $_wireload_file
        echo [format "%s%s" {Info: Reading in Wireload File } $_wireload_file]
      } else {
        echo [format "%s%s" [format "%s%s" {Warning: Wireload File } $_wireload_file] { Not Found.}]
      }
  }
  set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_dbdir {/my_}] $TDT_foundry_lib] {.}] $TDT_dbext]
  write_lib $TDT_foundry_lib -format db -output $_file_out
} else {
    echo [format "%s%s" [format "%s%s" [format "%s%s" {Info: No Custom Wireload File: } $TDT_custom_wireload ] { or Pass not greater than 1: } ] $TDT_pass]
}

exit
# end of file.

EOWLDCT
}

##--------------------------------------------------------------
sub dump_db_script {
  my $fileref = shift;
print $fileref <<'EODB';
# AFETC Generated Script - Edit with care
# Budget Compiler simple script
#
## assume that .synopsys_pt.setup is read already

# set the dbdir up for the proper pass.
set TDT_dbdir [format "%s%s" [format "%s%s"  $TDT_dbdir {.} ] $TDT_pass ]

# need to add dbdir to the path so everything can be found.
set _search_path [format "%s%s"  {./} $TDT_dbdir ]
set search_path [concat  $_search_path $search_path]

# only if we are at pass 1 or better do we bother.
# if we have a custom wireload file then use the my_vendor library file in the db directory
if { $TDT_pass >= 1} {
    if { [file exists $TDT_custom_wireload] } {
        echo "Info: Referencing Library with Custom Wireload Models"
        set _my_library [format "%s%s" [format "%s%s" {my_} $TDT_foundry_lib ] {.db} ]
        set link_library [concat $_my_library $link_library]
        set link_path $link_library
    } 
}

read_db $TDT_file
set _dc_shell_status [link]
    if { $_dc_shell_status == 0} {
        echo {Info: Expecting Design Link but it did not?}
        exit 1
    } else {
        echo {Info: Link OK}
    }

# assume that the user has build the constraints with both min and max, which
#  is not supported in Budget shell.  We must reset the design first for all timing
#  aspects, then read in the constraint file.  The constraint file must have in it a
#  check of the variable: synopsys_program_name which is equal to "budget_shell" around
#  all the minimum timings in order for this to work.
reset_design -timing
source -verbose $TDT_top_constraints

# now dump out into the log file what loops broken
# report_disable_timing

incr TDT_pass 
allocate_budget \
    -format dcsh \
    -interblock_logic \
    -level $TDT_level \
    -create_context \
    -write_context \
    -file_format_spec "$TDT_consdir/%D.$TDT_pass.$TDT_consext";

# now dump out the budget information so we have it also in the log file
check_budget -verbose

exit;
# end of file

EODB

}
##--------------------------------------------------------------
sub dump_pt_script {
  my $fileref = shift;
print $fileref <<'EOPT';
# AFETC Generated Script - Edit with care
# Prime Time simple script
#
## assume that .synopsys_pt.setup is read already

# the search path must be setup to see the database
set search_path [concat $TDT_dbdir $search_path]
set _file_in [format "%s%s"  [format "%s%s" [format "%s%s" [format "%s%s"  $TDT_des {.}] $TDT_pass] {.}] $TDT_dbext]
read_db $_file_in

# for layout this only reads the top level now we need to link the design.
set _dc_shell_status [link]
    if { $_dc_shell_status == 0} {
        echo {Info: Expecting Design Link but it did not?}
        exit 1
    } else {
        echo {Info: Link OK}
    }

# also to read anything else - this is a real PT pain.
set search_path [concat $TDT_sdfdir $search_path]
set _file_in [format "%s%s"  [format "%s%s"  $TDT_des {.}] $TDT_sdfext]
read_sdf -analysis_type single $_file_in

# grap the current level constraints file
set _file_in [format "%s%s"  [format "%s%s"  $TDT_des {.}] $TDT_conext]
source $_file_in

# Tells us what it things it is going to be able to do.
check_timing
report_analysis_coverage

# now disable the scan chain to do normal analysis
set_case_analysis 0 scantestmode

# for prelayout we must remove the reset pin from the analysis, post layout should have a clock tree?
set_false_path -from reset

# this reports the timing for the worst case nets of the sysclk group.
set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $TDT_des] {_with_sdf.}] $TDT_pass] {.rawtiming.rpt}]
redirect $_file_out {report_timing -path_type end -nosplit -group sysclk100 -max_paths 100000}

# hard coded for now
exec bin/parse_timing.pl $_file_out

# now dump out the report file we all can use.
set _file_in [format "%s%s"  $TDT_des {new_timing.dct}]
source $_file_in

exit;
# end of file

EOPT

}
##--------------------------------------------------------------
sub dump_fpm_script {
  my $fileref = shift;
print $fileref <<'EOFPM';
# AFETC Generated Script - Edit with care
# Floorplan Manager generic script
#
## assume that .synopsys_dc.setup is read already

# the search path must be setup to see the database
set TDT_dbdir [format "%s%s" [format "%s%s"  $TDT_dbdir {.} ] $TDT_pass ]

set _file_in [format "%s%s" [format "%s%s" [format "%s%s" [format "%s%s"  $TDT_dbdir {/} ] $TDT_des] {.}] $TDT_dbext]
read_db $_file_in

# for layout this only reads the top level now we need to link the design.
set _dc_shell_status [link]
    if { $_dc_shell_status == 0} {
        echo {Info: Expecting Design Link but it did not?}
        exit 1
    } else {
        echo {Info: Link OK}
    }

# now lets reset the design so we have no preconcieved ideas of what constraints are applied.
reset_design

# reset the design to the top and dump the DB so we have a match.
current_design $TDT_des

# Grab the SDF file
set search_path [concat $TDT_sdfdir $search_path]
set _file_in [format "%s%s" [format "%s%s" [format "%s%s" [format "%s%s"  $TDT_sdfdir {/} ] $TDT_des] {.}] $TDT_sdfext]
read_sdf -analysis_type single $_file_in

# now lets read in the physical data:
# first find all the PDEF files in the FP directory
set _pdef_list  [glob $TDT_phydir/*.PDEF]

# now lets interate over them finding the base name to use as the design name.
foreach _pdef_file $_pdef_list {
   echo [concat {Processing File: } $_pdef_file]
   set _design [file rootname [ file tail $_pdef_file]]
   read_clusters -design $_design $_pdef_file
}

# reset the design to the top and dump the DB so we have a match.
current_design $TDT_des

# now read in the setload data; make sure you translate it first.
set _file_in [format "%s%s" [format "%s%s" [format "%s%s" [format "%s%s"  $TDT_phydir {/} ] $TDT_des] {_setload.}] $TDT_conext]
source $_file_in

# grap the current level constraints file
set _file_in [format "%s%s"  [format "%s%s"  $TDT_des {.}] $TDT_conext]
source $_file_in

# now disable the scan chain to do normal analysis
set_case_analysis 0 scantestmode
set_false_path -from reset
set_false_path -from scantestmode

# this reports the timing for the worst case nets of the sysclk group.
set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $TDT_des] {_fpm_pre.}] $TDT_pass] {.qor.rpt}]
redirect $_file_out {report_qor}

# setup how you want the reoptimize to be performed.
set_critical_range 8.0 $TDT_des

set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $TDT_des] {_fpm_changes.}] $TDT_pass] {.rpt}]
set reoptimize_design_changed_list_file_name $_file_out

# now do a location based optimization
reoptimize_design -ignore_cell_area -map_effort high -tolerance_to_change high

set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $TDT_repdir {/}] $TDT_des] {_fpm_post.}] $TDT_pass] {.qor.rpt}]
redirect $_file_out {report_qor}

#now generate the improved outputs.
## somewhat hard coded it needs work - FIXUP

# increment pass as this is new.
incr TDT_pass
set _dir_out [format "%s%s"  [format "%s%s"  $TDT_fpdir {/files.}] $TDT_pass]
exec mkdir $_dir_out

set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  $_dir_out {/}] $TDT_des] {.v}]
write -hierarchy -format verilog -output $_file_out

set _dir_out [format "%s%s"  [format "%s%s"  $TDT_dbdir {.}] $TDT_pass]
exec mkdir $_dir_out

set _file_out [format "%s%s"  [format "%s%s"  [format "%s%s"  [format "%s%s"  $_dir_out {/}] $TDT_des] {.}] $TDT_dbext]
write -hierarchy -format db -output $_file_out

exit;
# end of file

EOFPM

}

##--------------------------------------------------------------
sub dump_formal_script {
  my $fileref = shift;
print $fileref <<'EOFORMAL';
# AFETC Generated Script - Edit with care
# Formality generic script
#
## assume that .synopsys_pt.setup is already

# read in your library specific stuff
source vlsidiv_pt.setup

# now read in all the default DB
# this example shows the 0.20u VLSI library defaults
read_db vsc1083.db
read_db vsc1083e.db
read_db vsc10p31.db
read_db vsc1083_memory.db

# our chip RAMS yours may vary
read_db ipxc01_ram.db

# the search path must be setup to see the database
set TDT_dbdir [format "%s%s%s"  $TDT_dbdir {.} [expr $TDT_pass - 2] ]
set search_path [concat $TDT_dbdir $search_path]

# create a reference container and reference design
create_container PreLayout
  set _file_in [format "%s%s%s"  $TDT_des {.} $TDT_dbext ]
  read_db _file_in
  set_reference_design PreLayout:/WORK/$TDT_des
  # now validate that it links:
  set _dc_shell_status [link $ref]
  if { $_dc_shell_status == 0} {
      echo {Info: Expecting Design Link but it did not?}
      exit 1
  } else {
      echo {Info: Link OK}
  }

# create a implemention container and reference design
set search_path [concat $TDT_phydir $search_path]
create_container PostLayout
  read_verilog -c PostLayout -netlist $TDT_srcfile
  set_implementation_design PostLayout:/WORK/$TDT_des
  set _dc_shell_status [link $impl]
  if { $_dc_shell_status == 0} {
      echo {Info: Expecting Design Link but it did not?}
      exit 1
  } else {
      echo {Info: Link OK}
  }


# check the design
verify

exit
# end of file

EOFORMAL

}

##--------------------------------------------------------------
sub dump_ungroup_dw_script {
  my $fileref = shift;
print $fileref <<'EOUDW';
# ungroup_dw.tcl - DC-Tcl proc to ungroup DW or non-DW cells
# chrispy@synopsys.com
#
# 6/10/99 initial release

proc ungroup_dw {args} {
  global sh_dev_null

  set results(-all_but_dw) 0
  set results(-hierarchical) 0
  parse_proc_arguments -args $args results

  set all_hier_cells [get_cells * -filter "@is_hierarchical == true"]
  set dw_cells ""
  set nondw_cells ""
  set nondw_designs ""

  foreach_in_collection this_cell $all_hier_cells {
    set this_design [get_designs [get_attribute -quiet $this_cell ref_name]]
    if {[string match "true" [get_attribute -quiet $this_design is_nmodule]]} {
      if {![string match "true" [get_attribute -quiet $this_design is_sequential]]} {
        set dw_cells [add_to_collection $dw_cells $this_cell]
      }
    } else {
      set nondw_cells [add_to_collection $nondw_cells $this_cell]
      set nondw_designs [add_to_collection -unique $nondw_designs $this_design]
    }
  }

  redirect $sh_dev_null {set orig_design [current_design]}

  # first, go into any non-DW designs if we're doing hierarchical ungrouping
  if {$results(-hierarchical)} {
    foreach_in_collection this_design $nondw_designs {
      redirect $sh_dev_null {current_design $this_design}
      switch $results(-all_but_dw) {
        0 {ungroup_dw -hier}
        1 {ungroup_dw -hier -all_but_dw}
      }
    }

    redirect $sh_dev_null {current_design $orig_design}
  }

  # now ungroup what we need to at this level
  switch $results(-all_but_dw) {
    0 {
      foreach_in_collection this_cell $dw_cells {
        echo "Ungrouping DW cell [get_object_name $this_cell] in [get_object_name $orig_design]..."
      }
      ungroup -flatten $dw_cells
    }
    1 {
      foreach_in_collection this_cell $nondw_cells {
        echo "Ungrouping non-DW cell [get_object_name $this_cell] in [get_object_name $orig_design]..."
      }
      ungroup $nondw_cells
    }
  }
}

define_proc_attributes ungroup_dw \
  -info "ungroup DesignWare or non-DesignWare cells" \
  -define_args \
  {
    {-all_but_dw "ungroup non-DW hierarchy cells" "" boolean optional}
    {-hierarchical "perform operation on subhierarchy as well" "" boolean optional}
  }
# end of file ungroup_dw.tcl
EOUDW

}
##--------------------------------------------------------------
sub dump_ungroup_dw2_script {
  my $fileref = shift;
print $fileref <<'EOU2DW';
# ungroup_dw2.tcl - DC-Tcl proc to ungroup DW or non-DW cells
proc ungroup_dw_2 {args} {
  global sh_dev_null

  set dw_cells [get_cells -hier * -filter "@DesignWare == true"]

  redirect $sh_dev_null {set orig_design [current_design]}


  foreach_in_collection this_cell $dw_cells {
     echo "Ungrouping DW cell [get_object_name $this_cell] in [get_object_name $orig_design]..."
     current_instance $this_cell
     current_instance ..
     ungroup -flatten $this_cell
     current_design $orig_design
  }

}
# end of file ungroup_dw_2.tcl
EOU2DW

}

##--------------------------------------------------------------
sub dump_check_dw_script {
  my $fileref = shift;
print $fileref <<'EOCKDW';
# check_dw.tcl - DC-Tcl proc to report on DW used
# NAME: check_dw
# MODE: dc_shell -tcl_mode OR dc_shell-t
#
# USAGE:
# Procedure "check_dw" looks through a large hierarchy for
# slow, or otherwise undesired, DesignWare implementations.
# To use it, save out the script and "source" the file in
# dc_shell-t. Invoke "check_dw" like any other Tcl command.
# The argument is any valid DesignWare implementation name.
# If omitted, the argument defaults to ripple-carry (rpl).
#
# EXAMPLE:    dc_shell-t> check_dw rpl
#
proc check_dw {{SLOW_IMPL rpl}} {
    set COUNT 0
    current_instance
    set BLOCK_COLL  [get_cells  -hierarchical  *      \
            -filter {@is_hierarchical == true}\
            ]
    foreach_in_collection  BLOCK_TAG   $BLOCK_COLL {
        set BLOCK_NAME  [get_object_name $BLOCK_TAG]
        set  IMPL_NAME  [get_attribute   $BLOCK_TAG  \
                synimpl   -quiet      \
                ]
        if {[string match $SLOW_IMPL $IMPL_NAME]} {
            echo "\nWarning:"
            echo "Block $BLOCK_NAME is \"$IMPL_NAME\"." 
            incr COUNT
        } else {
            echo "\nInformation:"
            echo "Checked block $BLOCK_NAME is \"$IMPL_NAME\"."
        }
    }
    echo "\nTotal of $COUNT warnings."
}

# end of file
EOCKDW
}

##--------------------------------------------------------------
sub dump_input_setup_script {
  my $fileref = shift;
print $fileref <<'EOINSU';
#Description: This PrimeTime process provides the setup delay relative
#             to different clock groups for all inputs.
#             SETUP_DELAY = data delay from input - clock delay + FF setup time
#
#Usage: pt_shell> source report_input_setup_delay.proc
#       pt_shell> report_input_setup_delay <output_file>
#

proc report_input_setup_delay {OutputFile} {

#create a file for the report
set outfile [open $OutputFile w ]
puts $outfile "The SETUP_DELAY is = data delay from input - clock delay + FF setup time" 
puts $outfile "" 
puts $outfile [format "%-20s %-40s %-25s %-12s" "STARTPOINT" "ENDPOINT" "ENDPOINT_CLOCK" "SETUP_DELAY"]
puts $outfile [format "%-20s %-40s %-25s %-12s" "==========" "========" "==============" "==========="]

set input_ports [all_inputs] 
foreach_in_collection input_port $input_ports {
    echo [format "%s%s" {Processing Input Port: } [query_objects $input_port]] 
    set path [get_timing_paths -from $input_port -to [all_registers -data] -nworst 1]

    # find start and endpoints 
    set start_point [get_attribute $path startpoint]
    set end_point [get_attribute $path endpoint]
    set StartPointName [get_attribute $start_point full_name]
    set EndPointName [get_attribute $end_point full_name]

    #get the name of the clock group of the end point
    set endpointclock [get_attribute $path endpoint_clock]
    set EndPointClockName [get_attribute $endpointclock full_name]
    if {$EndPointClockName ==""} {
        set EndPointClockName "No clock constraints"
    }

    set SetupTime [get_attribute $path endpoint_setup_time_value]

      
    #generate setup report
    puts $outfile [format "%-20s %-40s %-25s %-12s" $StartPointName $EndPointName $EndPointClockName $SetupTime]
    puts $outfile ""

}
close $outfile
}
# end of file
EOINSU
}

##--------------------------------------------------------------
sub dump_output_setup_script {
  my $fileref = shift;
print $fileref <<'EOUTSU';
#Description: This PrimeTime process provides the setup delay relative
#             to different clock groups for all inputs.
#             SETUP_DELAY = data delay from input - clock delay + FF setup time
#
#Usage: pt_shell> source report_input_setup_delay.proc
#       pt_shell> report_input_setup_delay (output_file)
#

proc report_output_setup_delay {OutputFile} {

#create a file for the report
set outfile [open $OutputFile w ]
puts $outfile "The OUTPUT_ARRIVAL is = FF Q -> Pin" 
puts $outfile "" 
puts $outfile [format "%-40s %-20s %-25s %-12s" "STARTPOINT"                    "ENDPOINT"            "StartPOINT_CLOCK"      "OUTPUT_ARRIVAL"]
puts $outfile [format "%-40s %-20s %-25s %-12s" "=============================" "================" "========================" "==========="]

set output_ports [all_outputs] 
foreach_in_collection output_port $output_ports { \
  set path [get_timing_paths -from [all_registers -output_pins] -to $output_port -nworst 1]

    # find start and endpoints 
    set start_point [get_attribute $path startpoint]
    set end_point [get_attribute $path endpoint]
    set StartPointName [get_attribute $start_point full_name]
    set EndPointName [get_attribute $end_point full_name]

    #get the name of the clock group of the end point
    set startpointclock [get_attribute $path startpoint_clock]
    set StartPointClockName [get_attribute $startpointclock full_name]
    if {$StartPointClockName ==""} {
        set StartPointClockName "No clock constraints"
    }

    set ArrivalTime [get_attribute $path arrival]

      
    #generate setup report
    puts $outfile [format "%-20s %-40s %-25s %-12s" $StartPointName $EndPointName $StartPointClockName $ArrivalTime]
    puts $outfile ""


}
close $outfile
}
# end of file
EOUTSU
}


##--------------------------------------------------------------
sub dump_timing_script {
  my $fileref = shift;
print $fileref <<'EODPTM';
#
# build_verilog_make.pl Generated Script - Edit with care
#  Dumps an Avant! specific timing report for the Avant tools
# 
proc DumpTiming { CurrentDesign {Pass 2} LayoutDir } {
   set _file [format "%s%s" [format "%s%s" [format "%s%s" $LayoutDir {/}] $CurrentDesign] {.timing.rpt}]
   redirect  $_file { report_clock -skew -nosplit }
   redirect -append $_file { echo 1 }
   redirect -append $_file { report_clock -attributes -nosplit }
   redirect -append $_file { echo 1 }
   redirect -append $_file { report_port -nosplit -verbose }
   redirect -append $_file { echo 1 }
   redirect -append $_file { report_timing_requirements }
   redirect -append $_file { echo 1 }
   redirect -append $_file {report_design -nosplit }
   redirect -append $_file { echo 1 }
}

# end of file dump_timing.tcl
EODPTM

}

##--------------------------------------------------------------
sub dump_designs {
  my $depthsref = shift;
  
  my $fileref = shift;
  my %ordered;
  my @ordered;
  foreach ( keys %$depthsref ) {
    push @{$ordered{ $depthsref->{$_}}}, $_;
  }
  foreach (reverse sort {$a <=> $b} keys %ordered) {
    push @ordered, @{$ordered{$_}};
  }
  foreach (sort {$a <=> $b} keys %ordered) {
    my $indent = '..' x ($_-1);
    print STDERR "Info: Level $_:\n$indent", join("\n$indent", @{$ordered{$_}}), "\n";
  }
  print $fileref "set TDT_ordered_designs { \\\n     ";
  print $fileref join(" \\\n     ", @ordered), " \\\n}\n";

  return pop @ordered; ## return the last design (top-most)
}

##--------------------------------------------------------------
sub dump_makeinc {
  my $makefile = shift;
  my $gthscr = shift;
  my $gtscr = shift;
  my $dcscr = shift;
  my $dbscr = shift;
  my $initcons = shift;
  my $dchier = shift;
  my $top = shift;
  my $fileref = shift;

  my $chip = FIXUP;

  print $fileref <<"EOINC";

# AFETC Generated Script - Edit with care
## Variables required by Makefile $makefile
##
## User should modify this script, it will not be over
##  written by another invocation of the AFETC script
## 
## 
## TOP Design Name (override this to make lower modules
TOP_DESIGN = $top

## the chip level name
CHIP_DESIGN = $chip

## Directories and file exts
##--------------------------
## RTL is the directory that rtl souce code will be found
RTLPATH = ../blm
# the include path is where to find the included files.  Will be added
#  to the search path.
INCLUDEPATH = ../blm
VLOGEXT = v

## GDB is the directory that dc_shell will expect to read GTECH db's from
GDBPATH = gdb
GDBEXT = db

## DB is the directory that dc_shell will write db's to
DBPATH = database
DBEXT = db

## CONSPATH is the directory that budget_shell will write constraints to
## and dc_shell will expect initial and top constraints to exist in
CONSPATH = constraint
CONEXT = dcc

TCONEXT = dct

## initial constraints file
INITCONS = $initcons

## LOGSPATH is the directory that log files will be written to
LOGSPATH = log
LOGEXT = log

## LAYOUTPATH is the directory that to layout files will be written to
LAYOUTPATH = layout

## LAYOUTPATH is the directory that to layout files will be written to
FLOORPLANPATH = fp

## REPSPATH = reports directory for any reports written from dc_shell
REPSPATH = reports

## Executables
##------------
## SYNOPSYS is only used in this Make include to help find
## paths to the executables
SYNOPSYS = /usr/synopsys/\${SYNOPSYS_VERSION}/

## ARCH is only used in this Make include file
GETARCH = \${SYNOPSYS}/admin/install/syn/bin/getarch
## HARD CODED BECAUSE IT DOESNT WORK
## ARCH = \$(GETARCH:sh)
ARCH = hpux10

## DCSH is the full path to the dc_shell executable
## DCSH = \${SYNOPSYS}/\${ARCH}/syn/bin/dc_shell
DCSH = run_synop dc_shell

## DCSH is the full path to the dc_shell executable
## DCTSH = \${SYNOPSYS}/\${ARCH}/syn/bin/dc_shell-t
DCTSH = run_synop dc_shell-t

## FMSH is the full path to the formality executable
## DCTSH = \${SYNOPSYS}/\${ARCH}/syn/bin/dc_shell-t
FMSH = run_synop fm_shell

## DBSH is the full path to the budget_shell executable
## DBSH = \${SYNOPSYS}/\${ARCH}/syn/bin/budget_shell
DBSH = run_synop budget_shell

## PTSH is the full path to the pt_shell executable
## PTSH = \${SYNOPSYS}/\${ARCH}/syn/bin/pt_shell
PTSH = run_synop pt_shell

## TXSCRIPT is the util to translate dc scripts into pt scripts
## TXSCRIPT = \${SYNOPSYS}/\${ARCH}/syn/bin/transcript
TXSCRIPT = run_synop transcript

## DCTXSCRIPT is the util to translate dc scripts into dct scripts
## DCTXSCRIPT = \${SYNOPSYS}/\${ARCH}/syn/bin/dc-transcript
DCTXSCRIPT = run_synop dc-transcript

## FOUNDRY_SCREEN is the util or script to Screen netlists
FOUNDRY_SCREEN = ./bin/vlsi_di22_screener.csh

## the Baseline Foundary library you are using, for the wireload models.
FOUNDRY_LIB = vcs1083

## Scripts
##--------
## GTHSCR is the script that should be run to perform
## the compilation on the hierarchy version of the design
## to ensure all the pieces are found and linked together.
## the groupding and ungrouping takes place within this script.
GTHSCR = $gthscr

## GTSCR is the script that should be run to perform
## the compilation on the design using dc-t shell to build
## the GTECH design. This script reads in the verilog from
## the designlist and subdesign list, links and rights out
## the GTECH database
GTSCR = $gtscr

## GTECHIER is a tcl file that contains variables that only
##  the designer could know how to change.  Such things as 
##  grouping and ungrouping and special cells for test.
GTECHIER = ${top}_hierarchy.tcl

## DCSCR is the script that should be run to perform
## the compilation on the design
DCSCR = $dcscr

## DCTSCR is the script that should be run to perform
## the compilation on the design using dc-t shell.
DCTSCR = $dcscr

## DCTSCR is the script that should be run to perform
## the compilation on the design using dc-t shell.
DCHSCR = $dchier

## DBSCR is the script that should be run to perform
## the budgeting on the design
DBSCR = $dbscr

## APSCR is the script that should be run to perform
## the Area and Power analysis on the design
APSCR = generic_area.dct

## TCSCR is the script that should be run to perform
## the Test Compiler Run for Scan insertion and stuff.
TCSCR = generic_tc.dct

## WLSCR is the script that should be run to build
## A local library that has the wireloads impressed upon it.
WLSCR = generic_buildwl.dct

## DCCSCR is the script that should be run to perform
## The linking of top and chip together
DCCSCR = $chip.dct

## TESTSCR is the script that should be run to perform
## the check_test functions and protocol development for TMAX
TESTSCR = $chip.test.dct

## LAYOUTSCR is the script that should be run to perform
## The linking of top and chip together
LAYOUTSCR = $chip.layout.dct

## FPSCR is the script that should be run to perform
## The linking of top and chip together
FPSCR = $chip.fp.dct

## FPMSCR is the script that should be run to perform
## Floorplan Manager links between floorplanning and layout.
FPMSCR = $chip.fpm.dct

## FPMSCR is the script that should be run to perform
## FMP optimization on pre-route designs.
## Floorplan Manager 
PREFPMSCR = $chip.pre_fpm.dct

## FMSCR is the script that should be run to perform
## Formality Equivilence Checking between prelayout and postlayout.
FMSCR = $chip.fm.dct

## XCELL is the script that should be run 
## to force the exclusion of cells this is very 
## library dependant
XCELL = excluded_cells.dct

## A file which contains a linked list of wireload files
WIRELOADS = generic_wireload.dct

## Sundry variables
##-----------------
## PASS is 0 for pre-budget >0 for post-budget
PASS = 0

## TIMINGPATHS is 10 for sake of having a number.  This is the number
##  of paths that are checked for timing checker.  The larger the number
##  the more paths validated.
TIMINGPATHS = 10

## End of Make include file
EOINC

}

##--------------------------------------------------------------
sub dump_README {
  my $fileref = shift;

  print $fileref <<"EOREADME";

##
## AFETC Generated Output
## 
## The Readme


afetc usage:

Common Make commands for this tool:

# First used to setup base directories which the tool expects
make setup

#if you want to clean up the directories to rerun over them.
make clean

# often used to build the first GTECH database which seeds the rest of the run.
make all_hier_gtech

# normal flow of make commands to build a chip database which is ready for layout.
make PASS=0 budgets.0
make PASS=0 2fp
make PASS=1 my_library
make PASS=1 budgets.1
make PASS=2 my_library
make PASS=2 all_hier
make PASS=3 scan
make PASS=3 chip
make PASS=3 to_layout
make PASS=3 2fp

# after you get the layout back use the following commands
make PASS=4 fpm_layout
make PASS=4 pt_layout

# if you did the FPM flow with the FP then use these commands to go to layout.
make PASS=4 fpm_fp
make PASS=5 chip
make PASS=5 to_layout

# now when you get stuff back you can run these comands
make PASS=6 fpm_layout
make PASS=6 pt_layout
make PASS=6 pre2postgate



## End of README
EOREADME

}

##--------------------------------------------------------------
## Main process
my %subs = ();

## Parse the command line and figure out where to bung stuff
my %args = @ARGV; ## command line arguments

## check for required args
die "Usage: $0 -d <designlist> OR -r <designlist>  [-m Makefile [-mi Makefile.inc]",
    " [-c <initcons.scr>] [-l <depth>]\n" 
  unless defined $args{'-d'} or defined $args{'-r'};

if (defined $args{'-d'}) {
    open(DESIGNLIST, "<$args{'-d'}") || 
        die "Cannot read design list $args{'-d'}\n";
    print "Using Designlist: ", $args{'-d'}, "\n";
} else {
    open(DESIGNLIST, "<$args{'-r'}") || 
        die "Cannot read design list $args{'-d'}\n";
    print "Using Designlist: ", $args{'-r'}, "\n";
}
create_subs \%subs, \*DESIGNLIST;
## print STDERR "Debug: Create Subs Returned: $status\n";
close DESIGNLIST;

my $top_design = scalar figure_top \%subs;
##print STDERR "Debug: Top design is $top_design\n";

my %depths; ## list keyed by design, value = depth of design (from top)
my $maxdepth = create_depths $top_design, \%subs, \%depths;
## print STDERR "Debug: Max Depth = $maxdepth\n";
$args{'-l'} = $maxdepth unless defined $args{'-l'};

$args{'-o'} = $top_design . '.ordered.tcl';
open(ORDERED,">$args{'-o'}") || die "Cannot create ordered dc file $args{'-o'}\n";
dump_designs \%depths, \*ORDERED;
close ORDERED;

$args{'-m'} = 'Makefile' unless defined $args{'-m'};
$args{'-mi'} = $args{'-m'}.'.inc' unless defined $args{'-mi'};

warn "Unable to create $args{'m'}\n", exit unless
  open(MAKEFILE, ">$args{'-m'}");
print MAKEFILE "## Makefile generated by $0 \\\n",
  "## ", join("\\\n## ", @ARGV), "\n";
dump_makefile \%subs, \%depths, $top_design, $args{'-mi'}, $args{'-l'}, $args{'-m'}, \*MAKEFILE;
close MAKEFILE;

$makertl = $args{'-m'} . '.RTL';
$makegate = $args{'-m'} . '.GATES';
$makelocal = $args{'-m'} . '.LOCAL';

# some default file names
$gt_global_script = 'gt_global.dct';
$gth_global_script = 'gth_global.dct';

# now dump out the supporing makefiles.
if (defined $args{'-r'}) {
    open(MAKEFILERTL, ">$makertl") || 
      die "Cannot Open for write Makefile $makegate\n";
    print STDERR "Building RTL Specific Makefile: ", $makertl, "\n";
    dump_rtl_makefile \%subs, \%depths, $top_design, $args{'-mi'}, $args{'-l'}, \*MAKEFILERTL;
    close MAKEFILERTL;

    if( ! -f $gt_global_script ) {
        warn "Creating DCT script file $gt_global_script\n";
        die "Unable to create $gt_global_script\n" unless
            open(GTSCR, ">$gt_global_script");
        dump_gt_script \*GTSCR;
        close GTSCR;
    } else {
        warn "DCT script file $gt_global_script exists, will not overwrite\n";
    }

    if( ! -f $gth_global_script ) {
        warn "Creating DCT script file $gth_global_script\n";
        die "Unable to create $gth_global_script\n" unless
            open(GTHSCR, ">$gth_global_script");
        dump_gth_script \*GTHSCR;
        close GTHSCR;
    } else {
        warn "DCT script file $gth_global_script exists, will not overwrite\n";
    }
    system("touch $makegate");
    system("touch $makelocal");
} elsif (defined $args{'-d'}) {
    open(MAKEFILEGATE, "> $makegate") || 
        die "Cannot Open for write Makefile $makegate\n";
    print "Building Gate Specific Makefile: ", $makegate, "\n";
    dump_gates_makefile \%subs, \%depths, $top_design, $args{'-mi'}, $args{'-l'}, \*MAKEFILEGATE;
    close MAKEFILEGATE;
    system("touch $makertl");
    system("touch $makelocal");

} else {
    system("touch $makertl");
    system("touch $makegate");
    system("touch $makelocal");
}


$args{'-s'} = 'dc_global.dct';
$dc_global_script = $args{'-s'};

if( ! -f $args{'-s'} ) {
    warn "Creating DCT script file $args{'-s'}\n";
    die "Unable to create $args{'-s'}\n" unless
      open(DCSCR, ">$args{'-s'}");
    dump_dct_script \*DCSCR;
    close DCSCR;
} else {
    warn "DCT script file $args{'-s'} exists, will not overwrite\n";
}

# should be more inteligent
$dc_hier_script = 'dch_global.dct';
if( ! -f $dc_hier_script ) {
  warn "Creating DCH script file $dc_hier_script\n";
  die "Unable to create $dc_hier_script\n" unless
    open(DCHSCR, "> $dc_hier_script");
  dump_dct_hier_script \*DCHSCR;
  close DCHSCR;
} else {
  warn "DCT script file $dc_hier_script exists, will not overwrite\n";
}

$args{'-c'} = $top_design . '.initial.dct' unless defined $args{'-c'};
if( ! -f $args{'-c'} ) {
  warn "Creating Initial constraints script file $args{'-c'}\n";
  die "Unable to create $args{'-c'}\n" unless
    open(CONSCR, ">$args{'-c'}");
  dump_init_cons \*CONSCR;
  close CONSCR;
} else {
  warn "Initial constraints script file $args{'-c'} exists, will not overwrite\n";
}


$db_global_script = 'db_global.dct';

if( ! -f $db_global_script ) {
  warn "Creating DB script file $db_global_script\n";
  die "Unable to create $db_global_script\n" unless
    open(DBSCR, ">$db_global_script");
  dump_db_script \*DBSCR;
  close DBSCR;
} else {
  warn "DB script file $db_global_script exists, will not overwrite\n";
}


# should be more inteligent
$gth_generic_script = 'gth_generic.dct';
if( ! -f $gth_generic_script ) {
    warn "Creating DCT script file $gth_generic_script\n";
    die "Unable to create $gth_generic_script\n" unless
        open(GTHGSCR, ">$gth_generic_script");
    dump_gth_generic_script \*GTHGSCR;
    close GTHGSCR;
}

# should be more inteligent
$dct_layout_script = 'generic_layout.dct';
if( ! -f $dct_layout_script ) {
  warn "Creating Layout script file $dct_layout_script\n";
  die "Unable to create $dct_layout_script\n" unless
    open(DCLSCR, "> $dct_layout_script");
  dump_dct_layout_script \*DCLSCR;
  close DCLSCR;
} else {
  warn "DCT script file $dct_layout_script exists, will not overwrite\n";
}

# should be more inteligent
$dct_fp_script = 'generic_fp.dct';
if( ! -f $dct_fp_script ) {
  warn "Creating Fp script file $dct_fp_script\n";
  die "Unable to create $dct_fp_script\n" unless
    open(DCFPSCR, "> $dct_fp_script");
  dump_dct_floorplan_script \*DCFPSCR;
  close DCFPSCR;
} else {
  warn "DCT script file $dct_fp_script exists, will not overwrite\n";
}

# should be more inteligent
$dct_test_script = 'generic_test.dct';
if( ! -f $dct_test_script ) {
  warn "Creating Test script file $dct_test_script\n";
  die "Unable to create $dct_test_script\n" unless
    open(DCFPSCR, "> $dct_test_script");
  dump_dct_test_script \*DCFPSCR;
  close DCFPSCR;
} else {
  warn "DCT script file $dct_test_script exists, will not overwrite\n";
}

# should be more inteligent
$dct_pt_script = 'generic_pt.dct';
if( ! -f $dct_pt_script ) {
  warn "Creating PT script file $dct_pt_script\n";
  die "Unable to create $dct_pt_script\n" unless
    open(DCPTSCR, "> $dct_pt_script");
  dump_dct_floorplan_script \*DCPTSCR;
  close DCPTSCR;
} else {
  warn "DCT script file $dct_pt_script exists, will not overwrite\n";
}

# should be more inteligent
$dct_area_script = 'generic_area.dct';
if( ! -f $dct_area_script ) {
  warn "Creating Area script file $dct_area_script\n";
  die "Unable to create $dct_area_script\n" unless
    open(DCASCR, "> $dct_area_script");
  dump_dct_area_script \*DCASCR;
  close DCASCR;
} else {
  warn "DCT script file $dct_area_script exists, will not overwrite\n";
}

# should be more inteligent
$dct_tc_script = 'generic_tc.dct';
if( ! -f $dct_tc_script ) {
  warn "Creating Test Compiler script file $dct_tc_script\n";
  die "Unable to create $dct_tc_script\n" unless
    open(TCSCR, "> $dct_tc_script");
  dump_tc_script \*TCSCR;
  close TCSCR;
} else {
  warn "DCT script file $dct_tc_script exists, will not overwrite\n";
}

# should be more inteligent
$scr_script = 'generic_compile.scr';
if( ! -f $scr_script ) {
  warn "Creating Generic Compile Script file $scr_script\n";
  die "Unable to create $scr_script\n" unless
    open(GCSCR, "> $scr_script");
  dump_generic_compile_scr \*GCSCR;
  close GCSCR;
} else {
  warn "Generic SCR script file $scr_script exists, will not overwrite\n";
}

# should be more inteligent
$hscr_script = 'generic_hier_compile.scr';
if( ! -f $hscr_script ) {
  warn "Creating Generic Hierarchy Compile S