JOIN US FOR A FREE HANDS-ON WORKSHOP THAT WILL EXPAND YOUR SKILLS AND STREAMLINE YOUR FPGA DESIGN PROCESS

Sponsored by:
VeriBest® ~ Luscombe Engineering ~ t2design ~ University of Colorado

9:00 a.m. to 4:00 p.m.
University of Colorado Integrated Teaching Labs, Boulder
8:30 am Continental Breakfast
12:00 p.m. Lunch (provided)

This tutorial is designed to provide an overview of the FPGA design process using VHDL. There will be a lecture presentation by one of the area's leading ASIC/FPGA design consulting firms, followed by a hands-on lab session for all attendees. The hands-on lab session is designed to take the user through a VHDL-based FPGA design flow, including design concept through FPGA place and route. The attendees will create a VHDL module of an ALU to complete the design. With a maximum of two attendees per workstation, each person is guaranteed an opportunity to work with the language and the tools to see how easy it is to use VHDL for FPGA design.

• Using HDLs for Effective Hardware Design
• The VHDL Design Flow Process for FPGA Design
• Introduction to the VHDL Language
• Synthesis for FPGA Design 77 Hands-on lab session to give you "real life" experience with the tools and processes

Tom Tessier is President of t2design, a local ASIC/FPGA design-consulting firm. Mr. Tessier's applied knowledge includes: VHDL, Verilog, numerous EDA design tools, and FPGA and ASIC libraries from a variety of sources. Engineers at t2design are experienced in a wide spectrum of electronic systems, including video, graphics, and microprocessors. Mr. Tessier has delivered over 50 days of training, focusing on HDL design methodologies throughout the US and Canada.

Hands-On Lab Session:

There will be an interactive lab session utilizing the NT Workstations of the Integrated Teaching Labs and the latest in FPGA design software including:

• FPGA design management using VeriBest Design View
• Graphical entry for VHDL using VeriBest Graphical High Level Design
• Text entry for VHDL using VeriBest HDL Writer
• Full design simulation and debug using VeriBest VI-IDL Simulator
• Design synthesis for a Xilinx FPGA using VeriBest FPGA Synthesis
  (powered by Synopsys FPGA Express)
• FPGA place and route using Xilinx MI Place and Route

Please call toll free 1-888-482-3322, press option 5 to register. Seating is limited, so register today!